Holistic Optimization Framework for FPGA Accelerators.

Jason Cong University of California, Los Angeles, USA http://cadlab.cs.ucla.edu/~cong/ https://scholar.google.com/citations?user=UVGe0gQAAAAJ https://dl.acm.org/profile/81452596992 https://zbmath.org/authors/?q=ai:cong.jason https://mathgenealogy.org/id.php?id=70473 https://en.wikipedia.org/wiki/Jason_Cong https://orcid.org/0000-0003-2887-6963 https://www.wikidata.org/entity/Q6162244 https://id.loc.gov/authorities/names/n2002162279 https://www.wikidata.org/entity/Q130808956

Stéphane Pouget Michael Lo Louis-Noël Pouchet Jason Cong Holistic Optimization Framework for FPGA Accelerators. 7:1-7:37 2026 January 31 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/3769307 db/journals/todaes/todaes31.html#PougetLPC26 streams/journals/todaes

Stefan Abi-Karam Rishov Sarkar Suhail Basalama Jason Cong Callie Hao FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs. ASP-DAC 2026 489-495 conf/aspdac/2026 https://doi.org/10.1109/ASP-DAC66049.2026.11420742 db/conf/aspdac/aspdac2026.html#AbiKaramSBCH26 streams/conf/aspdac Yang Zou 0001 Zijian Ding Chi Wang 0001 Yizhou Sun Jason Cong AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow. 183 2026 FPGA https://doi.org/10.1145/3748173.3779566 conf/fpga/2026 db/conf/fpga/fpga2026.html#0001D0SC26

Deming Chen Vijay Ganesh 0001 Weikai Li 0002 Yingyan Celine Lin Yong Liu Subhasish Mitra David Z. Pan Ruchir Puri Jason Cong Yizhou Sun Report for NSF Workshop on AI for Electronic Design Automation. 2026 January abs/2601.14541 CoRR https://doi.org/10.48550/arXiv.2601.14541 db/journals/corr/corr2601.html#abs-2601-14541 streams/journals/corr

Jiahao Zhang Zifan He Nicholas Fraser Michaela Blott Yizhou Sun Jason Cong FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design. 2026 January abs/2601.15710 CoRR https://doi.org/10.48550/arXiv.2601.15710 db/journals/corr/corr2601.html#abs-2601-15710 streams/journals/corr

Xiaoxuan Wang Han Zhang Haixin Wang 0003 Yidan Shi Ruoyan Li Kaiqiao Han Chenyi Tong Haoran Deng Renliang Sun Alexander Taylor 0002 Yanqiao Zhu 0001 Jason Cong Yizhou Sun Wei Wang 0010 ARLArena: A Unified Framework for Stable Agentic Reinforcement Learning. 2026 February abs/2602.21534 CoRR https://doi.org/10.48550/arXiv.2602.21534 db/journals/corr/corr2602.html#abs-2602-21534 streams/journals/corr

Deming Chen Jason Cong Azalia Mirhoseini Christos Kozyrakis Subhasish Mitra Jinjun Xiong Cliff Young Anima Anandkumar Michael L. Littman Aron Kirschen Sophia Shao Serge Leef Naresh R. Shanbhag Dejan S. Milojicic Michael Schulte Gert Cauwenberghs Jerry M. Chow Tri Dao Kailash Gopalakrishnan Richard Ho Hoshik Kim Kunle Olukotun David Z. Pan Mark Ren Dan Roth Aarti Singh Yizhou Sun Yusu Wang Yann LeCun Ruchir Puri AI+HW 2035: Shaping the Next Decade. 2026 March abs/2603.05225 CoRR https://doi.org/10.48550/arXiv.2603.05225 db/journals/corr/corr2603.html#abs-2603-05225 streams/journals/corr

Stéphane Pouget Louis-Noël Pouchet Jason Cong Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 26:1-26:44 2025 March 30 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/3711847 db/journals/todaes/todaes30.html#PougetPC25 streams/journals/todaes

Weikai Li 0002 Ding Wang Zijian Ding Atefeh Sohrabizadeh Zongyue Qin Jason Cong Yizhou Sun Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis. 18476-18484 2025 AAAI https://doi.org/10.1609/aaai.v39i17.34033 conf/aaai/2025 db/conf/aaai/aaai2025.html#0002WDSQCS25 Zongyue Qin Zifan He Neha Prakriya Jason Cong Yizhou Sun Dynamic-Width Speculative Beam Decoding for LLM Inference. 25056-25064 2025 AAAI https://doi.org/10.1609/aaai.v39i23.34690 conf/aaai/2025 db/conf/aaai/aaai2025.html#QinHPCS25 Daniel Bochen Tan Wan-Hsuan Lin Jason Cong Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. 921-929 2025 ASP-DAC https://doi.org/10.1145/3658617.3697778 conf/aspdac/2025 db/conf/aspdac/aspdac2025.html#TanLC25 Shuohao Ping Wan-Hsuan Lin Daniel Bochen Tan Jason Cong Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks. 1-7 2025 DAC https://doi.org/10.1109/DAC63849.2025.11133143 conf/dac/2025 db/conf/dac/dac2025.html#PingLTC25 streams/conf/dac Faaiq Waqar Jiahao Zhang Anni Lu Zifan He Jason Cong Shimeng Yu Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories. 1-7 2025 DAC https://doi.org/10.1109/DAC63849.2025.11132615 conf/dac/2025 db/conf/dac/dac2025.html#WaqarZLHCY25 streams/conf/dac Chengyue Wang 0002 Jiahao Zhang Yingquan Wu Jason Cong HP-FFT: A General High-Performance FFT Generator Using High-Level Synthesis. 19-23 2025 FCCM https://doi.org/10.1109/FCCM62733.2025.00026 conf/fccm/2025 db/conf/fccm/fccm2025.html#WangZWC25 Zifan He Anderson Truong Yingqi Cao Jason Cong InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs. 123-132 2025 FCCM https://doi.org/10.1109/FCCM62733.2025.00047 conf/fccm/2025 db/conf/fccm/fccm2025.html#HeTCC25 Huifeng Ke Sihao Liu Licheng Guo Zifan He Linghao Song Suhail Basalama Yuze Chi Tony Nowatzki Jason Cong NoH: NoC Compilation in High-Level Synthesis. 162-171 2025 FCCM https://doi.org/10.1109/FCCM62733.2025.00062 conf/fccm/2025 db/conf/fccm/fccm2025.html#KeLGHSBCNC25 Zifan He Hersh Gupta Huifeng Ke Jason Cong InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs. 44 2025 FPGA https://doi.org/10.1145/3706628.3708828 conf/fpga/2025 db/conf/fpga/fpga2025.html#HeGKC25 Suhail Basalama Jason Cong Stream-HLS: Towards Automatic Dataflow Acceleration. 103-114 2025 FPGA https://doi.org/10.1145/3706628.3708878 conf/fpga/2025 db/conf/fpga/fpga2025.html#BasalamaC25 Stéphane Pouget Louis-Noël Pouchet Jason Cong A Unified Framework for Automated Code Transformation and Pragma Insertion. 187-198 2025 FPGA https://doi.org/10.1145/3706628.3708873 conf/fpga/2025 db/conf/fpga/fpga2025.html#PougetPC25 Michael Lo Mau-Chung Frank Chang Jason Cong SAT-Accel: A Modern SAT Solver on a FPGA. 234-246 2025 FPGA https://doi.org/10.1145/3706628.3708869 conf/fpga/2025 db/conf/fpga/fpga2025.html#LoCC25 Wan-Hsuan Lin Daniel Bochen Tan Jason Cong Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms. 127-142 2025 HPCA https://doi.org/10.1109/HPCA61900.2025.00021 conf/hpca/2025 db/conf/hpca/hpca2025.html#LinTC25 Linfeng Du Jiawei Liang Jason Lau Yuze Chi Yutong Xie 0011 Chunyou Su Afzal Ahmad Zifan He Jake Ke Jinming Ge Jason Cong Wei Zhang 0012 Licheng Guo Automated Design Space Exploration in High-Level Physical Synthesis. 1-9 2025 ICCAD https://doi.org/10.1109/ICCAD66269.2025.11240757 conf/iccad/2025 db/conf/iccad/iccad2025.html#DuLLCXSAHKGCZG25 streams/conf/iccad Yannick Stade Wan-Hsuan Lin Jason Cong Robert Wille Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing. 1-9 2025 ICCAD https://doi.org/10.1109/ICCAD66269.2025.11240721 conf/iccad/2025 db/conf/iccad/iccad2025.html#StadeLCW25 streams/conf/iccad Zongyue Qin Ziniu Hu Zifan He Neha Prakriya Jason Cong Yizhou Sun Optimized Multi-Token Joint Decoding With Auxiliary Model for LLM Inference. 2025 ICLR https://openreview.net/forum?id=ZHhBawo3k5 conf/iclr/2025 db/conf/iclr/iclr2025.html#QinHHPCS25 Chengyue Wang 0002 Xiaofan Zhang 0001 Jason Cong James C. Hoe Reconfigurable Stream Network Architecture. 1848-1866 2025 ISCA https://doi.org/10.1145/3695053.3731088 conf/isca/2025 db/conf/isca/isca2025.html#00020CH25 Wan-Hsuan Lin Jason Cong ML-QLS: Multilevel Quantum Layout Synthesis. 55-63 2025 ISPD https://doi.org/10.1145/3698364.3705358 conf/ispd/2025 db/conf/ispd/ispd2025.html#LinC25 Jason Cong Invited: Coping with Interconnects. 222-230 2025 ISPD https://doi.org/10.1145/3698364.3712622 conf/ispd/2025 db/conf/ispd/ispd2025.html#Cong25 Zifan He Yingqi Cao Zongyue Qin Neha Prakriya Yizhou Sun Jason Cong HMT: Hierarchical Memory Transformer for Efficient Long Context Language Processing. 8068-8089 2025 NAACL (Long Papers) https://doi.org/10.18653/v1/2025.naacl-long.410 https://aclanthology.org/2025.naacl-long.410/ conf/naacl/2025-1 db/conf/naacl/naacl2025-1.html#HeCQPSC25 streams/conf/naacl

Faaiq G. Waqar Jiahao Zhang Anni Lu Zifan He Jason Cong Shimeng Yu Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories. 2025 January abs/2501.06921 CoRR https://doi.org/10.48550/arXiv.2501.06921 db/journals/corr/corr2501.html#abs-2501-06921 streams/journals/corr

Suhail Basalama Jason Cong Stream-HLS: Towards Automatic Dataflow Acceleration. 2025 January abs/2501.09118 CoRR https://doi.org/10.48550/arXiv.2501.09118 db/journals/corr/corr2501.html#abs-2501-09118 streams/journals/corr

Stéphane Pouget Michael Lo Louis-Noël Pouchet Jason Cong Holistic Optimization Framework for FPGA Accelerators. 2025 January abs/2501.09242 CoRR https://doi.org/10.48550/arXiv.2501.09242 db/journals/corr/corr2501.html#abs-2501-09242 streams/journals/corr

Zifan He Anderson Truong Yingqi Cao Jason Cong InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs. 2025 February abs/2502.08807 CoRR https://doi.org/10.48550/arXiv.2502.08807 db/journals/corr/corr2502.html#abs-2502-08807 streams/journals/corr

Sihao Liu Jake Ke Tony Nowatzki Jason Cong Demystifying FPGA Hard NoC Performance. 2025 March abs/2503.10861 CoRR https://doi.org/10.48550/arXiv.2503.10861 db/journals/corr/corr2503.html#abs-2503-10861 streams/journals/corr

Neha Prakriya Zijian Ding Yizhou Sun Jason Cong LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning. 2025 April abs/2504.21187 CoRR https://doi.org/10.48550/arXiv.2504.21187 db/journals/corr/corr2504.html#abs-2504-21187 streams/journals/corr

Hanyu Wang Xinrui Wu Zijian Ding Su Zheng Chengyue Wang 0002 Tony Nowatzki Yizhou Sun Jason Cong LLM-DSE: Searching Accelerator Parameters with LLM Agents. 2025 May abs/2505.12188 CoRR https://doi.org/10.48550/arXiv.2505.12188 db/journals/corr/corr2505.html#abs-2505-12188 streams/journals/corr

Yannick Stade Wan-Hsuan Lin Jason Cong Robert Wille Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing. 2025 May abs/2505.22715 CoRR https://doi.org/10.48550/arXiv.2505.22715 db/journals/corr/corr2505.html#abs-2505-22715 streams/journals/corr

Zijian Ding Tung Nguyen Weikai Li 0002 Aditya Grover Yizhou Sun Jason Cong Iceberg: Enhancing HLS Modeling with Synthetic Data. 2025 July abs/2507.09948 CoRR https://doi.org/10.48550/arXiv.2507.09948 db/journals/corr/corr2507.html#abs-2507-09948 streams/journals/corr

Yongxiang Liu Yuchun Ma Eren Kurshan Glenn Reinman Jason Cong Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. 2025 August abs/2508.13158 CoRR https://doi.org/10.48550/arXiv.2508.13158 db/journals/corr/corr2508.html#abs-2508-13158 streams/journals/corr

Stefan Abi-Karam Rishov Sarkar Suhail Basalama Jason Cong Callie Hao FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs. 2025 October abs/2510.20981 CoRR https://doi.org/10.48550/arXiv.2510.20981 db/journals/corr/corr2510.html#abs-2510-20981 streams/journals/corr

Zifan He Shengyu Ye Rui Ma Yang Wang Jason Cong LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs. 2025 November abs/2511.06174 CoRR https://doi.org/10.48550/arXiv.2511.06174 db/journals/corr/corr2511.html#abs-2511-06174 streams/journals/corr

Chengyue Wang 0002 Wesley Pang Xinrui Wu Gregory Jun Luis Romero Endri Taka Diana Marculescu Tony Nowatzki Pranathi Vasireddy Joseph Melber Deming Chen Jason Cong Can Asymmetric Tile Buffering Be Beneficial? 2025 November abs/2511.16041 CoRR https://doi.org/10.48550/arXiv.2511.16041 db/journals/corr/corr2511.html#abs-2511-16041 streams/journals/corr

Daniel Bochen Tan Dolev Bluvstein Mikhail D. Lukin Jason Cong Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. 1281 2024 March 8 Quantum https://doi.org/10.22331/q-2024-03-14-1281 db/journals/quantum/quantum8.html#TanBLC24

Liqiang Lu Zizhang Luo Size Zheng 0001 Jieming Yin Jason Cong Yun Liang 0001 Jianwei Yin Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. 1177-1190 2024 April 43 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2023.3337208 db/journals/tcad/tcad43.html#LuLZYCLY24

Atefeh Sohrabizadeh Yunsheng Bai Yizhou Sun Jason Cong Harnessing GNNs for Robust Representation Learning in High-Level Synthesis. 114-127 2024 December 1 IEEE Trans. Circuits Syst. Artif. Intell. 2 https://doi.org/10.1109/TCASAI.2024.3485522 db/journals/tcasai/tcasai1.html#SohrabizadehBSC24 streams/journals/tcasai

Moazin Khatti Xingyu Tian Ahmad Sedigh Baroughi Akhil Raj Baranwal Yuze Chi Licheng Guo Jason Cong Zhenman Fang PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. 42:1-42:31 2024 September 17 ACM Trans. Reconfigurable Technol. Syst. 3 https://doi.org/10.1145/3676849 https://www.wikidata.org/entity/Q130828043 db/journals/trets/trets17.html#KhattiTBBCGCF24 streams/journals/trets

Jinming Zhuang Jason Lau Hanchen Ye Zhuoping Yang Shixin Ji Jack Lo Kristof Denolf Stephen Neuendorffer Alex K. Jones Jingtong Hu Yiyu Shi 0001 Deming Chen Jason Cong Peipei Zhou 0001 CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. 51:1-51:31 2024 September 17 ACM Trans. Reconfigurable Technol. Syst. 3 https://doi.org/10.1145/3686163 https://www.wikidata.org/entity/Q130934964 db/journals/trets/trets17.html#ZhuangLYYJLDNJHSCCZ24 streams/journals/trets

Neha Prakriya Yuze Chi Suhail Basalama Linghao Song Jason Cong TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. 966-980 2024 ASPLOS (3) https://doi.org/10.1145/3620666.3651347 https://www.wikidata.org/entity/Q130851364 conf/asplos/2024-3 db/conf/asplos/asplos2024-3.html#PrakriyaCBSC24 Karl Marrett Keivan Moradi Chris Sin Park Ming Yan 0006 Chris Choi Muye Zhu Masood Akram Sumit Nanda Qing Xue Hyun-Seung Mun Adriana E. Gutierrez Mitchell Rudd Brian Zingg Gabrielle Magat Kathleen Wijaya Hongwei Dong X. William Yang Jason Cong Gossamer: Scaling Image Processing and Reconstruction to Whole Brains. 3-19 2024 BI (1) https://doi.org/10.1007/978-981-96-3294-7_1 conf/brain/2024-1 db/conf/brain/brain2024-1.html#MarrettMPYCZANXMGRZMWDY24 streams/conf/brain Karl Marrett Keivan Moradi Chris Sin Park Ming Yan 0006 Chris Choi Muye Zhu Masood Akram Sumit Nanda Qing Xue Hyun-Seung Mun Adriana E. Gutierrez Mitchell Rudd Brian Zingg Gabrielle Magat Kathleen Wijaya Hongwei Dong X. William Yang Jason Cong High Throughput Training Label Generation from Whole Brain Images. 151-163 2024 BI (2) https://doi.org/10.1007/978-981-96-3297-8_12 conf/brain/2024-2 db/conf/brain/brain2024-2.html#MarrettMPYCZANXMGRZMWDY24a streams/conf/brain Tianqi Zhang Neha Prakriya Sumukh Pinge Jason Cong Tajana Rosing SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering. 56:1-56:6 2024 DAC https://doi.org/10.1145/3649329.3657354 https://www.wikidata.org/entity/Q131129391 conf/dac/2024 db/conf/dac/dac2024.html#ZhangPPCR24 Hanrui Wang 0002 Daniel Bochen Tan Pengyu Liu Yilian Liu Jiaqi Gu 0002 Jason Cong Song Han 0003 Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas. 306:1-306:6 2024 DAC https://doi.org/10.1145/3649329.3658470 conf/dac/2024 db/conf/dac/dac2024.html#0002TLL0C024 Daniel Bochen Tan Shuohao Ping Jason Cong Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. 1-6 2024 DATE https://doi.org/10.23919/DATE58400.2024.10546763 conf/date/2024 db/conf/date/date2024.html#TanPC24 Hanyu Wang Jason Cong Giovanni De Micheli Quantum State Preparation Using an Exact CNOT Synthesis Formulation. 1-6 2024 DATE https://doi.org/10.23919/DATE58400.2024.10546633 conf/date/2024 db/conf/date/date2024.html#WangCM24 Zifan He Linghao Song Robert F. Lucas Jason Cong LevelST: Stream-based Accelerator for Sparse Triangular Solver. 67-77 2024 FPGA https://doi.org/10.1145/3626202.3637568 https://www.wikidata.org/entity/Q130880907 conf/fpga/2024 db/conf/fpga/fpga2024.html#HeSLC24 Stéphane Pouget Louis-Noël Pouchet Jason Cong Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 184 2024 FPGA https://doi.org/10.1145/3626202.3637593 https://www.wikidata.org/entity/Q130828066 conf/fpga/2024 db/conf/fpga/fpga2024.html#PougetPC24 Hanyu Wang Daniel Bochen Tan Jason Cong Quantum State Preparation Circuit Optimization Exploiting Don't Cares. 31:1-31:9 2024 ICCAD https://doi.org/10.1145/3676536.3676646 conf/iccad/2024 db/conf/iccad/iccad2024.html#WangTC24 Atefeh Sohrabizadeh Wan-Hsuan Lin Daniel Bochen Tan Madelyn Cain Sheng-Tao Wang Mikhail D. Lukin Jason Cong GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set. 62:1-62:6 2024 ICCAD https://doi.org/10.1145/3676536.3697129 conf/iccad/2024 db/conf/iccad/iccad2024.html#SohrabizadehLTC24 Zijian Ding Atefeh Sohrabizadeh Weikai Li 0002 Zongyue Qin Yizhou Sun Jason Cong Efficient Task Transfer for HLS DSE. 133:1-133:9 2024 ICCAD https://doi.org/10.1145/3676536.3676723 conf/iccad/2024 db/conf/iccad/iccad2024.html#DingS0QSC24 Jason Lau Yuanlong Xiao Yutong Xie 0011 Yuze Chi Linghao Song Shaojie Xiang Michael Lo Zhiru Zhang Jason Cong Licheng Guo RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. 170:1-170:11 2024 ICCAD https://doi.org/10.1145/3676536.3676649 conf/iccad/2024 db/conf/iccad/iccad2024.html#LauX0CSXLZCG24 Hanrui Wang 0002 Pengyu Liu Daniel Bochen Tan Yilian Liu Jiaqi Gu 0002 David Z. Pan Jason Cong Umut A. Acar Song Han 0003 Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. 293-309 2024 ISCA https://doi.org/10.1109/ISCA59077.2024.00030 conf/isca/2024 db/conf/isca/isca2024.html#WangLTLGPCAH24 streams/conf/isca Jason Cong Scheduling and Physical Design. 219-225 2024 ISPD https://doi.org/10.1145/3626184.3635290 https://www.wikidata.org/entity/Q130818914 conf/ispd/2024 db/conf/ispd/ispd2024.html#Cong24 Yunsheng Bai Atefeh Sohrabizadeh Zijian Ding Rongjian Liang Weikai Li 0002 Ding Wang Haoxing Ren Yizhou Sun Jason Cong Learning to Compare Hardware Designs for High-Level Synthesis. 2 2024 MLCAD https://doi.org/10.1145/3670474.3685940 https://doi.org/10.1109/MLCAD62225.2024.10740257 conf/mlcad/2024 db/conf/mlcad/mlcad2024.html#BaiSDL0WRSC24 Zongyue Qin Yunsheng Bai Atefeh Sohrabizadeh Zijian Ding Ziniu Hu Yizhou Sun Jason Cong Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. 14 2024 MLCAD https://doi.org/10.1145/3670474.3685952 https://doi.org/10.1109/MLCAD62225.2024.10740204 https://www.wikidata.org/entity/Q130870478 conf/mlcad/2024 db/conf/mlcad/mlcad2024.html#QinBSDHSC24

Hanyu Wang Bochen Tan Jason Cong Giovanni De Micheli Quantum State Preparation Using an Exact CNOT Synthesis Formulation. 2024 abs/2401.01009 CoRR https://doi.org/10.48550/arXiv.2401.01009 db/journals/corr/corr2401.html#abs-2401-01009

Daniel Bochen Tan Shuohao Ping Jason Cong Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. 2024 abs/2401.13807 CoRR https://doi.org/10.48550/arXiv.2401.13807 db/journals/corr/corr2401.html#abs-2401-13807

Stéphane Pouget Louis-Noël Pouchet Jason Cong Enhancing High-Level Synthesis with Automated Pragma Insertion and Code Transformation Framework. 2024 abs/2405.03058 CoRR https://doi.org/10.48550/arXiv.2405.03058 db/journals/corr/corr2405.html#abs-2405-03058

Zifan He Zongyue Qin Neha Prakriya Yizhou Sun Jason Cong HMT: Hierarchical Memory Transformer for Long Context Language Processing. 2024 abs/2405.06067 CoRR https://doi.org/10.48550/arXiv.2405.06067 db/journals/corr/corr2405.html#abs-2405-06067

Stéphane Pouget Louis-Noël Pouchet Jason Cong Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. 2024 abs/2405.12304 CoRR https://doi.org/10.48550/arXiv.2405.12304 db/journals/corr/corr2405.html#abs-2405-12304

Daniel Bochen Tan Wan-Hsuan Lin Jason Cong Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. 2024 abs/2405.15095 CoRR https://doi.org/10.48550/arXiv.2405.15095 db/journals/corr/corr2405.html#abs-2405-15095

Wan-Hsuan Lin Jason Cong ML-QLS: Multilevel Quantum Layout Synthesis. 2024 abs/2405.18371 CoRR https://doi.org/10.48550/arXiv.2405.18371 db/journals/corr/corr2405.html#abs-2405-18371

Zongyue Qin Yunsheng Bai Atefeh Sohrabizadeh Zijian Ding Ziniu Hu Yizhou Sun Jason Cong Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. 2024 abs/2406.09606 CoRR https://doi.org/10.48550/arXiv.2406.09606 db/journals/corr/corr2406.html#abs-2406-09606

Zongyue Qin Ziniu Hu Zifan He Neha Prakriya Jason Cong Yizhou Sun Multi-Token Joint Speculative Decoding for Accelerating Large Language Model Inference. 2024 abs/2407.09722 CoRR https://doi.org/10.48550/arXiv.2407.09722 db/journals/corr/corr2407.html#abs-2407-09722 streams/journals/corr

Zijian Ding Atefeh Sohrabizadeh Weikai Li 0002 Zongyue Qin Yizhou Sun Jason Cong Efficient Task Transfer for HLS DSE. 2024 abs/2408.13270 CoRR https://doi.org/10.48550/arXiv.2408.13270 db/journals/corr/corr2408.html#abs-2408-13270 streams/journals/corr

Neha Prakriya Jui-Nan Yen Cho-Jui Hsieh Jason Cong Accelerating Large Language Model Pretraining via LFR Pedagogy: Learn, Focus, and Review. 2024 abs/2409.06131 CoRR https://doi.org/10.48550/arXiv.2409.06131 db/journals/corr/corr2409.html#abs-2409-06131 streams/journals/corr

Yunsheng Bai Atefeh Sohrabizadeh Zijian Ding Rongjian Liang Weikai Li 0002 Ding Wang Haoxing Ren Yizhou Sun Jason Cong Learning to Compare Hardware Designs for High-Level Synthesis. 2024 abs/2409.13138 CoRR https://doi.org/10.48550/arXiv.2409.13138 db/journals/corr/corr2409.html#abs-2409-13138 streams/journals/corr

Zongyue Qin Zifan He Neha Prakriya Jason Cong Yizhou Sun Dynamic-Width Speculative Beam Decoding for Efficient LLM Inference. 2024 abs/2409.16560 CoRR https://doi.org/10.48550/arXiv.2409.16560 db/journals/corr/corr2409.html#abs-2409-16560 streams/journals/corr

Jason Lau Yuanlong Xiao Yutong Xie 0011 Yuze Chi Linghao Song Shaojie Xiang Michael Lo Zhiru Zhang Jason Cong Licheng Guo RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. 2024 abs/2410.13079 CoRR https://doi.org/10.48550/arXiv.2410.13079 db/journals/corr/corr2410.html#abs-2410-13079 streams/journals/corr

Weikai Li 0002 Ding Wang Zijian Ding Atefeh Sohrabizadeh Zongyue Qin Jason Cong Yizhou Sun Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis. 2024 abs/2410.19225 CoRR https://doi.org/10.48550/arXiv.2410.19225 db/journals/corr/corr2410.html#abs-2410-19225 streams/journals/corr

Chengyue Wang 0002 Xiaofan Zhang 0001 Jason Cong James C. Hoe Addressing Architectural Obstacles for Overlay with Stream Network Abstraction. 2024 abs/2411.17966 CoRR https://doi.org/10.48550/arXiv.2411.17966 db/journals/corr/corr2411.html#abs-2411-17966 streams/journals/corr

Yuze Chi Weikang Qiao Atefeh Sohrabizadeh Jie Wang 0022 Jason Cong Democratizing Domain-Specific Computing. 74-85 2023 66 Commun. ACM 1 https://doi.org/10.1145/3524108 db/journals/cacm/cacm66.html#ChiQSWC23

Gert Cauwenberghs Jason Cong X. Sharon Hu Siddharth Joshi 0001 Subhasish Mitra Wolfgang Porod H.-S. Philip Wong Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. 561-574 2023 June 111 Proc. IEEE 6 https://doi.org/10.1109/JPROC.2023.3276941 db/journals/pieee/pieee111.html#CauwenberghsCHJMPW23

Zhe Chen 0030 Garrett J. Blair Chengdi Cao Jim Zhou Daniel Aharoni Peyman Golshani Hugh T. Blair Jason Cong FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications. 169-179 2023 April 17 IEEE Trans. Biomed. Circuits Syst. 2 https://doi.org/10.1109/TBCAS.2023.3268130 db/journals/tbcas/tbcas17.html#ChenBCZAGBC23

Young Kyu Choi Yuze Chi Jason Lau Jason Cong TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. 2423-2427 2023 July 42 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2022.3216544 db/journals/tcad/tcad42.html#ChoiCLC23

Weikang Qiao Licheng Guo Zhenman Fang Mau-Chung Frank Chang Jason Cong TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs. 404-419 2023 April - June 11 IEEE Trans. Emerg. Top. Comput. 2 https://doi.org/10.1109/TETC.2022.3228575 db/journals/tetc/tetc11.html#QiaoGFCC23

Young Kyu Choi Carlos Santillana Yujia Shen Adnan Darwiche Jason Cong FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis. 18:1-18:22 2023 June 16 ACM Trans. Reconfigurable Technol. Syst. 2 https://doi.org/10.1145/3561514 https://www.wikidata.org/entity/Q130813363 db/journals/trets/trets16.html#ChoiSSDC23

Suhail Basalama Atefeh Sohrabizadeh Jie Wang 0022 Licheng Guo Jason Cong FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. 23:1-23:32 2023 June 16 ACM Trans. Reconfigurable Technol. Syst. 2 https://doi.org/10.1145/3570928 https://www.wikidata.org/entity/Q130808958 db/journals/trets/trets16.html#BasalamaSWGC23

Licheng Guo Pongstorn Maidee Yun Zhou Chris Lavin Eddie Hung Wuxi Li Jason Lau Weikang Qiao Yuze Chi Linghao Song Yuanlong Xiao Alireza Kaviani Zhiru Zhang Jason Cong RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. 59:1-59:30 2023 December 16 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3593025 https://www.wikidata.org/entity/Q130819848 db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23

Licheng Guo Yuze Chi Jason Lau Linghao Song Xingyu Tian Moazin Khatti Weikang Qiao Jie Wang 0022 Ecenur Ustun Zhenman Fang Zhiru Zhang Jason Cong TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. 63:1-63:31 2023 December 16 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3609335 https://www.wikidata.org/entity/Q130938275 db/journals/trets/trets16.html#GuoCLSTKQWUFZC23

Chen Zhang 0001 Guangyu Sun 0003 Zhenman Fang Peipei Zhou 0001 Jason Cong Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. 47-48 2023 ACM TUR-C https://doi.org/10.1145/3603165.3607390 conf/acmturc/2023 db/conf/acmturc/acmturc2023.html#00010F0C23 Suhail Basalama Jie Wang 0022 Jason Cong A Comprehensive Automated Exploration Framework for Systolic Array Designs. 1-6 2023 DAC https://doi.org/10.1109/DAC56929.2023.10248016 conf/dac/2023 db/conf/dac/dac2023.html#BasalamaWC23 Jason Cong Lightning Talk: Scaling Up Quantum Compilation - Challenges and Opportunities. 1-2 2023 DAC https://doi.org/10.1109/DAC56929.2023.10247677 conf/dac/2023 db/conf/dac/dac2023.html#Cong23 Wan-Hsuan Lin Jason Kimko Bochen Tan Nikolaj S. Bjørner Jason Cong Scalable Optimal Layout Synthesis for NISQ Quantum Processors. 1-6 2023 DAC https://doi.org/10.1109/DAC56929.2023.10247760 conf/dac/2023 db/conf/dac/dac2023.html#LinKTBC23 Zizhang Luo Liqiang Lu Size Zheng 0001 Jieming Yin Jason Cong Jianwei Yin Yun Liang 0001 Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. 1-6 2023 DAC https://doi.org/10.1109/DAC56929.2023.10247743 conf/dac/2023 db/conf/dac/dac2023.html#LuoLZYCYL23 Moazin Khatti Xingyu Tian Yuze Chi Licheng Guo Jason Cong Zhenman Fang PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. 12-22 2023 FCCM https://doi.org/10.1109/FCCM57271.2023.00011 conf/fccm/2023 db/conf/fccm/fccm2023.html#KhattiTCGCF23 Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong HMLib: Efficient Data Transfer for HLS Using Host Memory. 50 2023 FPGA https://doi.org/10.1145/3543622.3573157 https://www.wikidata.org/entity/Q130963470 conf/fpga/2023 db/conf/fpga/fpga2023.html#LoCQCC23 Jinming Zhuang Jason Lau Hanchen Ye Zhuoping Yang Yubo Du Jack Lo Kristof Denolf Stephen Neuendorffer Alex K. Jones Jingtong Hu Deming Chen Jason Cong Peipei Zhou 0001 CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. 153-164 2023 FPGA https://doi.org/10.1145/3543622.3573210 https://www.wikidata.org/entity/Q130935326 conf/fpga/2023 db/conf/fpga/fpga2023.html#ZhuangLYYDLDNJH23 Linghao Song Licheng Guo Suhail Basalama Yuze Chi Robert F. Lucas Jason Cong Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. 247-258 2023 FPGA https://doi.org/10.1145/3543622.3573182 conf/fpga/2023 db/conf/fpga/fpga2023.html#SongGBCLC23 Neha Prakriya Yu Yang 0007 Baharan Mirzasoleiman Cho-Jui Hsieh Jason Cong NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training. 8-15 2023 HotStorage https://doi.org/10.1145/3599691.3603404 https://www.wikidata.org/entity/Q130978126 conf/hotstorage/2023 db/conf/hotstorage/hotstorage2023.html#PrakriyaYMHC23 Atefeh Sohrabizadeh Yunsheng Bai Yizhou Sun Jason Cong Robust GNN-Based Representation Learning for HLS. 1-9 2023 ICCAD https://doi.org/10.1109/ICCAD57390.2023.10323853 conf/iccad/2023 db/conf/iccad/iccad2023.html#SohrabizadehBSC23 Yunsheng Bai Atefeh Sohrabizadeh Zongyue Qin Ziniu Hu Yizhou Sun Jason Cong Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs. 2023 NeurIPS http://papers.nips.cc/paper_files/paper/2023/hash/8dfc3a2720a4112243a285b98e0d4415-Abstract-Datasets_and_Benchmarks.html conf/nips/2023 db/conf/nips/neurips2023.html#BaiSQHSC23

Jinming Zhuang Jason Lau Hanchen Ye Zhuoping Yang Yubo Du Jack Lo Kristof Denolf Stephen Neuendorffer Alex K. Jones Jingtong Hu Deming Chen Jason Cong Peipei Zhou 0001 CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. 2023 abs/2301.02359 CoRR https://doi.org/10.48550/arXiv.2301.02359 db/journals/corr/corr2301.html#abs-2301-02359

Jason Cong Michalis Romesis Joseph R. Shinnerl Kenton Sze Min Xie 0004 Locality and Utilization in Placement Suboptimality. 2023 abs/2305.16413 CoRR https://doi.org/10.48550/arXiv.2305.16413 db/journals/corr/corr2305.html#abs-2305-16413

Daniel Bochen Tan Dolev Bluvstein Mikhail D. Lukin Jason Cong Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. 2023 abs/2306.03487 CoRR https://doi.org/10.48550/arXiv.2306.03487 db/journals/corr/corr2306.html#abs-2306-03487

Shichang Zhang Atefeh Sohrabizadeh Cheng Wan 0005 Zijie Huang 0002 Ziniu Hu Yewen Wang Yingyan Lin 0001 Jason Cong Yizhou Sun A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware. 2023 abs/2306.14052 CoRR https://doi.org/10.48550/arXiv.2306.14052 db/journals/corr/corr2306.html#abs-2306-14052

Neha Prakriya Yuze Chi Suhail Basalama Linghao Song Jason Cong TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. 2023 abs/2311.10189 CoRR https://doi.org/10.48550/arXiv.2311.10189 db/journals/corr/corr2311.html#abs-2311-10189

Hanrui Wang 0002 Pengyu Liu Bochen Tan Yilian Liu Jiaqi Gu 0002 David Z. Pan Jason Cong Umut A. Acar Song Han 0003 FPQA-C: A Compilation Framework for Field Programmable Qubit Array. 2023 abs/2311.15123 CoRR https://doi.org/10.48550/arXiv.2311.15123 db/journals/corr/corr2311.html#abs-2311-15123

Hanrui Wang 0002 Bochen Tan Pengyu Liu Yilian Liu Jiaqi Gu 0002 Jason Cong Song Han 0003 Q-Pilot: Field Programmable Quantum Array Compilation with Flying Ancillas. 2023 abs/2311.16190 CoRR https://doi.org/10.48550/arXiv.2311.16190 db/journals/corr/corr2311.html#abs-2311-16190

Wan-Hsuan Lin Bochen Tan Murphy Yuezhen Niu Jason Kimko Jason Cong Domain-Specific Quantum Architecture Optimization. 624-637 2022 12 IEEE J. Emerg. Sel. Topics Circuits Syst. 3 https://doi.org/10.1109/JETCAS.2022.3202870 db/journals/esticas/esticas12.html#LinTNKC22

Atefeh Sohrabizadeh Cody Hao Yu Min Gao 0003 Jason Cong AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators. 32:1-32:27 2022 27 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/3494534 https://www.wikidata.org/entity/Q114071114 db/journals/todaes/todaes27.html#SohrabizadehYGC22

Zhe Chen 0030 Hugh T. Blair Jason Cong Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction. 44:1-44:19 2022 27 ACM Trans. Design Autom. Electr. Syst. 5 https://doi.org/10.1145/3495006 https://www.wikidata.org/entity/Q130419269 db/journals/todaes/todaes27.html#ChenBC22

Jason Cong Jason Lau Gai Liu Stephen Neuendorffer Peichen Pan Kees A. Vissers Zhiru Zhang FPGA HLS Today: Successes, Challenges, and Opportunities. 51:1-51:42 2022 15 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3530775 https://www.wikidata.org/entity/Q130825784 db/journals/trets/trets15.html#CongLLNPVZ22

Yuanhao Wu Faruk V. Mutlu Yuezhou Liu Edmund Yeh Ran Liu 0010 Catalin Iordache Justas Balcas Harvey B. Newman Raimondas Sirvinskas Michael Lo Sichen Song Jason Cong Lixia Zhang 0001 Sankalpa Timilsina Susmit Shannigrahi Chengyu Fan Davide Pesavento Junxiao Shi Lotfi Benmohamed N-DISE: NDN-based data distribution for large-scale data-intensive science. 103-113 2022 ICN https://doi.org/10.1145/3517212.3558087 conf/acmicn/2022 db/conf/acmicn/icn2022.html#WuMLYLIBNSLSCZT22 Atefeh Sohrabizadeh Yuze Chi Jason Cong StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. 1-8 2022 CICC https://doi.org/10.1109/CICC53496.2022.9772832 conf/cicc/2022 db/conf/cicc/cicc2022.html#SohrabizadehCC22 Atefeh Sohrabizadeh Yunsheng Bai Yizhou Sun Jason Cong Automated accelerator optimization aided by graph neural networks. 55-60 2022 DAC https://doi.org/10.1145/3489517.3530409 conf/dac/2022 db/conf/dac/dac2022.html#SohrabizadehBSC22 Linghao Song Yuze Chi Licheng Guo Jason Cong Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. 211-216 2022 DAC https://doi.org/10.1145/3489517.3530420 conf/dac/2022 db/conf/dac/dac2022.html#SongCGC22 Yunsheng Bai Atefeh Sohrabizadeh Yizhou Sun Jason Cong Improving GNN-based accelerator design automation with meta learning. 1347-1350 2022 DAC https://doi.org/10.1145/3489517.3530629 https://www.wikidata.org/entity/Q130895967 conf/dac/2022 db/conf/dac/dac2022.html#BaiSSC22 Suhail Basalama Atefeh Sohrabizadeh Jie Wang 0022 Jason Cong A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. 1-2 2022 FCCM https://doi.org/10.1109/FCCM53951.2022.9786198 conf/fccm/2022 db/conf/fccm/fccm2022.html#BasalamaSWC22 Weikang Qiao Licheng Guo Zhenman Fang Mau-Chung Frank Chang Jason Cong TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. 1 2022 FCCM https://doi.org/10.1109/FCCM53951.2022.9786209 conf/fccm/2022 db/conf/fccm/fccm2022.html#QiaoGFCC22 Licheng Guo Pongstorn Maidee Yun Zhou Chris Lavin Jie Wang 0022 Yuze Chi Weikang Qiao Alireza Kaviani Zhiru Zhang Jason Cong RapidStream: Parallel Physical Implementation of FPGA HLS Designs. 1-12 2022 FPGA https://doi.org/10.1145/3490422.3502361 https://www.wikidata.org/entity/Q130827390 conf/fpga/2022 db/conf/fpga/fpga2022.html#GuoMZ00CQKZC22 Atefeh Sohrabizadeh Yunsheng Bai Yizhou Sun Jason Cong Automated Accelerator Optimization Aided by Graph Neural Networks. 50 2022 FPGA https://doi.org/10.1145/3490422.3502330 conf/fpga/2022 db/conf/fpga/fpga2022.html#SohrabizadehBSC22 Linghao Song Yuze Chi Atefeh Sohrabizadeh Young-kyu Choi Jason Lau Jason Cong Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. 65-77 2022 FPGA https://doi.org/10.1145/3490422.3502357 conf/fpga/2022 db/conf/fpga/fpga2022.html#SongCSCLC22 Atefeh Sohrabizadeh Yuze Chi Jason Cong SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. 156 2022 FPGA https://doi.org/10.1145/3490422.3502332 conf/fpga/2022 db/conf/fpga/fpga2022.html#SohrabizadehCC22 Yuze Chi Licheng Guo Jason Cong Accelerating SSSP for Power-Law Graphs. 190-200 2022 FPGA https://doi.org/10.1145/3490422.3502358 https://www.wikidata.org/entity/Q130866255 conf/fpga/2022 db/conf/fpga/fpga2022.html#ChiGC22 Linghao Song Yuze Chi Jason Cong PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. 76-80 2022 ICASSP https://doi.org/10.1109/ICASSP43922.2022.9746473 conf/icassp/2022 db/conf/icassp/icassp2022.html#SongCC22 Bochen Tan Dolev Bluvstein Mikhail D. Lukin Jason Cong Qubit Mapping for Reconfigurable Atom Arrays. 107:1-107:9 2022 ICCAD https://doi.org/10.1145/3508352.3549331 https://ieeexplore.ieee.org/document/10069573 https://www.wikidata.org/entity/Q130925587 conf/iccad/2022 db/conf/iccad/iccad2022.html#TanBLC22 Zhe Chen 0030 Jim Zhou Garrett J. Blair Hugh T. Blair Jason Cong Efficient Kernels for Real-Time Position Decoding from In Vivo Calcium Images. 1872-1876 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937945 conf/iscas/2022 db/conf/iscas/iscas2022.html#ChenZBBC22 Sihao Liu Jian Weng 0002 Dylan Kupsh Atefeh Sohrabizadeh Zhengrong Wang Licheng Guo Jiuyang Liu Maxim Zhulin Rishabh Mani Lucheng Zhang Jason Cong Tony Nowatzki OverGen: Improving FPGA Usability through Domain-specific Overlay Generation. 35-56 2022 MICRO https://doi.org/10.1109/MICRO56248.2022.00018 https://www.wikidata.org/entity/Q130813077 conf/micro/2022 db/conf/micro/micro2022.html#Liu0KSWGLZMZCN22

Weikang Qiao Licheng Guo Zhenman Fang Mau-Chung Frank Chang Jason Cong TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. 2022 abs/2205.07991 CoRR https://doi.org/10.48550/arXiv.2205.07991 db/journals/corr/corr2205.html#abs-2205-07991

Wan-Hsuan Lin Bochen Tan Murphy Yuezhen Niu Jason Kimko Jason Cong Domain-Specific Quantum Architecture Optimization. 2022 abs/2207.14482 CoRR https://doi.org/10.48550/arXiv.2207.14482 db/journals/corr/corr2207.html#abs-2207-14482

Licheng Guo Yuze Chi Jason Lau Linghao Song Xingyu Tian Moazin Khatti Weikang Qiao Jie Wang 0022 Ecenur Ustun Zhenman Fang Zhiru Zhang Jason Cong TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. 2022 abs/2209.02663 CoRR https://doi.org/10.48550/arXiv.2209.02663 db/journals/corr/corr2209.html#abs-2209-02663

Yuze Chi Weikang Qiao Atefeh Sohrabizadeh Jie Wang 0022 Jason Cong Democratizing Domain-Specific Computing. 2022 abs/2209.02951 CoRR https://doi.org/10.48550/arXiv.2209.02951 db/journals/corr/corr2209.html#abs-2209-02951

Linghao Song Licheng Guo Suhail Basalama Yuze Chi Robert F. Lucas Jason Cong Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. 2022 abs/2209.14350 CoRR https://doi.org/10.48550/arXiv.2209.14350 db/journals/corr/corr2209.html#abs-2209-14350

Bochen Tan Jason Cong Optimality Study of Existing Quantum Computing Layout Synthesis Tools. 1363-1373 2021 70 IEEE Trans. Computers 9 https://doi.org/10.1109/TC.2020.3009140 db/journals/tc/tc70.html#TanC21

Zhe Chen 0030 Garrett J. Blair Hugh T. Blair Jason Cong Fast Calcium Trace Extraction for Large-Field-of-View Miniscope. 1-5 2021 BioCAS https://doi.org/10.1109/BioCAS49922.2021.9644936 conf/biocas/2021 db/conf/biocas/biocas2021.html#ChenBBC21 Zhe Chen 0030 Garrett J. Blair Changliang Guo Daniel Aharoni Hugh T. Blair Jason Cong Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope. 1 2021 BioCAS https://doi.org/10.1109/BioCAS49922.2021.9645015 conf/biocas/2021 db/conf/biocas/biocas2021.html#ChenBGABC21 Weikang Qiao Jihun Oh Licheng Guo Mau-Chung Frank Chang Jason Cong FANS: FPGA-Accelerated Near-Storage Sorting. 106-114 2021 FCCM https://doi.org/10.1109/FCCM51124.2021.00020 conf/fccm/2021 db/conf/fccm/fccm2021.html#QiaoOGCC21 Yuze Chi Licheng Guo Jason Lau Young-kyu Choi Jie Wang 0022 Jason Cong Extending High-Level Synthesis for Task-Parallel Programs. 204-213 2021 FCCM https://doi.org/10.1109/FCCM51124.2021.00032 conf/fccm/2021 db/conf/fccm/fccm2021.html#ChiGLC0C21 Saranyu Chattopadhyay Florian Lonsing Luca Piccolboni Deepraj Soni Peng Wei 0004 Xiaofan Zhang 0001 Yuan Zhou Luca P. Carloni Deming Chen Jason Cong Ramesh Karri Zhiru Zhang Caroline Trippel Clark W. Barrett Subhasish Mitra Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. 42-52 2021 FMCAD https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_12 conf/fmcad/2021 db/conf/fmcad/fmcad2021.html#ChattopadhyayLP21 Licheng Guo Yuze Chi Jie Wang 0022 Jason Lau Weikang Qiao Ecenur Ustun Zhiru Zhang Jason Cong AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. 81-92 2021 FPGA https://doi.org/10.1145/3431920.3439289 https://www.wikidata.org/entity/Q130869028 conf/fpga/2021 db/conf/fpga/fpga2021.html#GuoC0LQUZC21 Jie Wang 0022 Licheng Guo Jason Cong AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. 93-104 2021 FPGA https://doi.org/10.1145/3431920.3439292 https://www.wikidata.org/entity/Q130840964 conf/fpga/2021 db/conf/fpga/fpga2021.html#0022GC21 Young-kyu Choi Yuze Chi Weikang Qiao Nikola Samardzic Jason Cong HBM Connect: High-Performance HLS Interconnect for FPGA HBM. 116-126 2021 FPGA https://doi.org/10.1145/3431920.3439301 https://www.wikidata.org/entity/Q130833415 conf/fpga/2021 db/conf/fpga/fpga2021.html#ChoiCQSC21 Atefeh Sohrabizadeh Cody Hao Yu Min Gao 0003 Jason Cong AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. 147 2021 FPGA https://doi.org/10.1145/3431920.3439464 https://www.wikidata.org/entity/Q130837416 conf/fpga/2021 db/conf/fpga/fpga2021.html#SohrabizadehYGC21 Yuze Chi Licheng Guo Young-kyu Choi Jie Wang 0022 Jason Cong Extending High-Level Synthesis for Task-Parallel Programs. 225 2021 FPGA https://doi.org/10.1145/3431920.3439470 conf/fpga/2021 db/conf/fpga/fpga2021.html#ChiGC0C21 Peipei Zhou 0001 Jiayi Sheng Cody Hao Yu Peng Wei 0004 Jie Wang 0022 Di Wu 0010 Jason Cong MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. 273-279 2021 FPGA https://doi.org/10.1145/3431920.3439304 https://www.wikidata.org/entity/Q131022323 conf/fpga/2021 db/conf/fpga/fpga2021.html#0001SYWWWC21 Bochen Tan Jason Cong Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper. 1-8 2021 ICCAD https://doi.org/10.1109/ICCAD51958.2021.9643554 conf/iccad/2021 db/conf/iccad/iccad2021.html#TanC21 Jason Cong From Parallelization to Customization - Challenges and Opportunities. 682 2021 IPDPS https://doi.org/10.1109/IPDPS49936.2021.00077 conf/ipps/2021 db/conf/ipps/ipdps2021.html#Cong21 Liqiang Lu Naiqing Guan Yuyue Wang 0001 Liancheng Jia Zizhang Luo Jieming Yin Jason Cong Yun Liang 0001 TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. 720-733 2021 ISCA https://doi.org/10.1109/ISCA52012.2021.00062 conf/isca/2021 db/conf/isca/isca2021.html#LuGWJLYC021

Liqiang Lu Naiqing Guan Yuyue Wang 0001 Liancheng Jia Zizhang Luo Jieming Yin Jason Cong Yun Liang 0001 TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. 2021 abs/2105.01892 CoRR https://arxiv.org/abs/2105.01892 db/journals/corr/corr2105.html#abs-2105-01892

Saranyu Chattopadhyay Florian Lonsing Luca Piccolboni Deepraj Soni Peng Wei 0004 Xiaofan Zhang 0001 Yuan Zhou Luca P. Carloni Deming Chen Jason Cong Ramesh Karri Zhiru Zhang Caroline Trippel Clark W. Barrett Subhasish Mitra Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. 2021 abs/2108.06081 CoRR https://arxiv.org/abs/2108.06081 db/journals/corr/corr2108.html#abs-2108-06081

Bochen Tan Jason Cong Optimal Qubit Mapping with Simultaneous Gate Absorption. 2021 abs/2109.06445 CoRR https://arxiv.org/abs/2109.06445 db/journals/corr/corr2109.html#abs-2109-06445

Linghao Song Yuze Chi Atefeh Sohrabizadeh Young-kyu Choi Jason Lau Jason Cong Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. 2021 abs/2109.11081 CoRR https://arxiv.org/abs/2109.11081 db/journals/corr/corr2109.html#abs-2109-11081

Linghao Song Yuze Chi Jason Cong Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. 2021 abs/2110.04280 CoRR https://arxiv.org/abs/2110.04280 db/journals/corr/corr2110.html#abs-2110-04280

Atefeh Sohrabizadeh Yuze Chi Jason Cong SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation. 2021 abs/2111.05936 CoRR https://arxiv.org/abs/2111.05936 db/journals/corr/corr2111.html#abs-2111-05936

Atefeh Sohrabizadeh Yunsheng Bai Yizhou Sun Jason Cong Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks. 2021 abs/2111.08848 CoRR https://arxiv.org/abs/2111.08848 db/journals/corr/corr2111.html#abs-2111-08848

Linghao Song Yuze Chi Licheng Guo Jason Cong Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. 2021 abs/2111.12555 CoRR https://arxiv.org/abs/2111.12555 db/journals/corr/corr2111.html#abs-2111-12555

Jie Wang 0022 Jason Cong Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. 2021 abs/2111.14252 CoRR https://arxiv.org/abs/2111.14252 db/journals/corr/corr2111.html#abs-2111-14252

Giovanni De Micheli Antun Domic Massimiliano Di Ventra Martin Roettler Jason Cong 2019 DAC Roundtable. 100-114 2020 37 IEEE Des. Test 3 https://doi.org/10.1109/MDAT.2020.2968279 db/journals/dt/dt37.html#MicheliDVRC20

Yijin Guan Guangyu Sun 0003 Zhihang Yuan Xingchen Li Ningyi Xu Shu Chen Jason Cong Yuan Xie 0001 Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. 931-943 2020 69 IEEE Trans. Computers 7 https://doi.org/10.1109/TC.2020.2981080 db/journals/tc/tc69.html#GuanSYLXCCX20

Young-kyu Choi Yuze Chi Jie Wang 0022 Jason Cong FLASH: Fast, Parallel, and Accurate Simulator for HLS. 4828-4841 2020 39 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2020.2970597 db/journals/tcad/tcad39.html#ChoiCWC20

Meng Li 0016 William Hsu Xiaodong Xie Jason Cong Wen Gao 0001 SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network. 2289-2301 2020 39 IEEE Trans. Medical Imaging 7 https://doi.org/10.1109/TMI.2020.2968472 https://www.wikidata.org/entity/Q92962798 db/journals/tmi/tmi39.html#LiHXCG20

Yuze Chi Jason Cong Exploiting Computation Reuse for Stencil Accelerators. 1-6 2020 DAC https://doi.org/10.1109/DAC18072.2020.9218680 conf/dac/2020 db/conf/dac/dac2020.html#ChiC20 Licheng Guo Jason Lau Yuze Chi Jie Wang 0022 Cody Hao Yu Zhe Chen 0030 Zhiru Zhang Jason Cong Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. 1-6 2020 DAC https://doi.org/10.1109/DAC18072.2020.9218718 conf/dac/2020 db/conf/dac/dac2020.html#GuoLC0YCZC20 Eshan Singh Florian Lonsing Saranyu Chattopadhyay Maxwell Strange Peng Wei 0004 Xiaofan Zhang 0001 Yuan Zhou Deming Chen Jason Cong Priyanka Raina Zhiru Zhang Clark W. Barrett Subhasish Mitra A-QED Verification of Hardware Accelerators. 1-6 2020 DAC https://doi.org/10.1109/DAC18072.2020.9218715 conf/dac/2020 db/conf/dac/dac2020.html#SinghLCS0ZZCCRZ20 Michael Lo Zhenman Fang Jie Wang 0022 Peipei Zhou 0001 Mau-Chung Frank Chang Jason Cong Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. 157-166 2020 FCCM https://doi.org/10.1109/FCCM48280.2020.00029 conf/fccm/2020 db/conf/fccm/fccm2020.html#LoFWZCC20 Jiajie Li Yuze Chi Jason Cong HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. 51-57 2020 FPGA https://doi.org/10.1145/3373087.3375320 https://www.wikidata.org/entity/Q130855559 conf/fpga/2020 db/conf/fpga/fpga2020.html#LiCC20 Atefeh Sohrabizadeh Jie Wang 0022 Jason Cong End-to-End Optimization of Deep Learning Applications. 133-139 2020 FPGA https://doi.org/10.1145/3373087.3375321 https://www.wikidata.org/entity/Q130977513 conf/fpga/2020 db/conf/fpga/fpga2020.html#SohrabizadehWC20 Licheng Guo Jason Lau Yuze Chi Jie Wang 0022 Cody Hao Yu Zhe Chen 0030 Zhiru Zhang Jason Cong Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. 311 2020 FPGA https://doi.org/10.1145/3373087.3375332 https://www.wikidata.org/entity/Q130837403 conf/fpga/2020 db/conf/fpga/fpga2020.html#GuoLCWYCZC20 Zhe Chen 0030 Garrett J. Blair Hugh T. Blair Jason Cong CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time. 318 2020 FPGA https://doi.org/10.1145/3373087.3375358 conf/fpga/2020 db/conf/fpga/fpga2020.html#ChenBBC20 Yi-Hsiang Lai Hongbo Rong Size Zheng 0001 Weihao Zhang Xiuping Cui Yunshan Jia Jie Wang 0022 Brendan Sullivan Zhiru Zhang Yun Liang 0001 Youhui Zhang Jason Cong Nithin George Jose Alvarez Christopher J. Hughes Pradeep Dubey SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. 73:1-73:9 2020 ICCAD https://doi.org/10.1145/3400302.3415644 https://ieeexplore.ieee.org/document/9256583 conf/iccad/2020 db/conf/iccad/iccad2020.html#LaiRZZCJ0SZ0ZCG20 Bochen Tan Jason Cong Optimal Layout Synthesis for Quantum Computing. 137:1-137:9 2020 ICCAD https://doi.org/10.1145/3400302.3415620 https://ieeexplore.ieee.org/document/9256696 https://www.wikidata.org/entity/Q130912954 conf/iccad/2020 db/conf/iccad/iccad2020.html#TanC20 Jason Lau Aishwarya Sivaraman Qian Zhang 0020 Muhammad Ali Gulzar Jason Cong Miryung Kim HeteroRefactor: refactoring for heterogeneous computing with FPGA. 493-505 2020 ICSE https://doi.org/10.1145/3377811.3380340 https://ieeexplore.ieee.org/document/9283938 https://www.wikidata.org/entity/Q130855585 conf/icse/2020 db/conf/icse/icse2020.html#LauSZGCK20 Nikola Samardzic Weikang Qiao Vaibhav Aggarwal Mau-Chung Frank Chang Jason Cong Bonsai: High-Performance Adaptive Merge Tree Sorting. 282-294 2020 ISCA https://doi.org/10.1109/ISCA45697.2020.00033 https://www.wikidata.org/entity/Q130970149 conf/isca/2020 db/conf/isca/isca2020.html#SamardzicQACC20 Zhe Chen 0030 Garrett J. Blair Hugh T. Blair Jason Cong BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices. 217-222 2020 ISLPED https://doi.org/10.1145/3370748.3406552 conf/islped/2020 db/conf/islped/islped2020.html#ChenBBC20

Bochen Tan Jason Cong Optimality Study of Existing Quantum Computing Layout Synthesis Tools. 2020 abs/2002.09783 CoRR https://arxiv.org/abs/2002.09783 db/journals/corr/corr2002.html#abs-2002-09783

Bochen Tan Jason Cong Optimal Layout Synthesis for Quantum Computing. 2020 abs/2007.15671 CoRR https://arxiv.org/abs/2007.15671 db/journals/corr/corr2007.html#abs-2007-15671

Yuze Chi Licheng Guo Young-kyu Choi Jie Wang 0022 Jason Cong Extending High-Level Synthesis for Task-Parallel Programs. 2020 abs/2009.11389 CoRR https://arxiv.org/abs/2009.11389 db/journals/corr/corr2009.html#abs-2009-11389

Atefeh Sohrabizadeh Cody Hao Yu Min Gao 0003 Jason Cong AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. 2020 abs/2009.14381 CoRR https://arxiv.org/abs/2009.14381 db/journals/corr/corr2009.html#abs-2009-14381

Young-kyu Choi Yuze Chi Jie Wang 0022 Licheng Guo Jason Cong When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. 2020 abs/2010.06075 CoRR https://arxiv.org/abs/2010.06075 db/journals/corr/corr2010.html#abs-2010-06075

Yanghyo Rod Kim Boyu Hu Yuan Du Wei-Han Cho Rulin Huang Adrian Tang 0002 Huan-Neng Ron Chen Chewnpu Jou Jason Cong Tatsuo Itoh Mau-Chung Frank Chang A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. 1600-1612 2019 54 IEEE J. Solid State Circuits 6 https://doi.org/10.1109/JSSC.2019.2896413 https://www.wikidata.org/entity/Q128358170 db/journals/jssc/jssc54.html#KimHDCHTCJCIC19

Jason Cong Zhenman Fang Muhuan Huang Peng Wei 0004 Di Wu 0010 Cody Hao Yu Customizable Computing - From Single Chip to Datacenters. 185-203 2019 107 Proc. IEEE 1 https://doi.org/10.1109/JPROC.2018.2876372 https://www.wikidata.org/entity/Q128835198 db/journals/pieee/pieee107.html#CongFHWWY19

Shuo Li 0007 Nong Xiao 0001 Peng Wang 0025 Guangyu Sun 0003 Xiaoyang Wang 0006 Yiran Chen 0001 Hai Helen Li Jason Cong Tao Zhang 0032 RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. 239-254 2019 68 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2018.2868368 https://www.wikidata.org/entity/Q129298829 db/journals/tc/tc68.html#LiXWSWCLCZ19

Chen Zhang 0001 Guangyu Sun 0003 Zhenman Fang Peipei Zhou 0001 Peichen Pan Jason Cong Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. 2072-2085 2019 38 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2017.2785257 https://www.wikidata.org/entity/Q129067848 db/journals/tcad/tcad38.html#ZhangSFZPC19

Young-kyu Choi Jason Cong Zhenman Fang Yuchen Hao Glenn Reinman Peng Wei 0004 In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms. 4:1-4:20 2019 12 ACM Trans. Reconfigurable Technol. Syst. 1 https://doi.org/10.1145/3294054 https://www.wikidata.org/entity/Q128350378 db/journals/trets/trets12.html#ChoiCFHRW18

Zhenman Fang Farnoosh Javadi Jason Cong Glenn Reinman Understanding Performance Gains of Accelerator-Rich Architectures. 239-246 2019 ASAP https://doi.org/10.1109/ASAP.2019.00013 conf/asap/2019 db/conf/asap/asap2019.html#FangJCR19 Xuechao Wei Yun Liang 0001 Jason Cong Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. 125 2019 DAC https://doi.org/10.1145/3316781.3317875 https://ieeexplore.ieee.org/document/8806999 https://www.wikidata.org/entity/Q130866243 conf/dac/2019 db/conf/dac/dac2019.html#Wei0C19 Weikang Qiao Zhenman Fang Mau-Chung Frank Chang Jason Cong An FPGA-Based BWT Accelerator for Bzip2 Data Compression. 96-99 2019 FCCM https://doi.org/10.1109/FCCM.2019.00023 conf/fccm/2019 db/conf/fccm/fccm2019.html#QiaoFCC19 Licheng Guo Jason Lau Zhenyuan Ruan Peng Wei 0004 Jason Cong Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. 127-135 2019 FCCM https://doi.org/10.1109/FCCM.2019.00027 conf/fccm/2019 db/conf/fccm/fccm2019.html#GuoLR0C19 Zhe Chen 0030 Hugh T. Blair Jason Cong LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization. 104-109 2019 FPGA https://doi.org/10.1145/3289602.3293919 https://www.wikidata.org/entity/Q130871136 conf/fpga/2019 db/conf/fpga/fpga2019.html#ChenBC19 Xuechao Wei Yun Liang 0001 Peng Zhang 0007 Cody Hao Yu Jason Cong Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. 120 2019 FPGA https://doi.org/10.1145/3289602.3293947 conf/fpga/2019 db/conf/fpga/fpga2019.html#Wei0ZYC19 Yuze Chi Young-kyu Choi Jason Cong Jie Wang 0022 Rapid Cycle-Accurate Simulator for High-Level Synthesis. 178-183 2019 FPGA https://doi.org/10.1145/3289602.3293918 conf/fpga/2019 db/conf/fpga/fpga2019.html#ChiCCW19 Jie Liu 0072 Jason Cong Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis. 187 2019 FPGA https://doi.org/10.1145/3289602.3293969 conf/fpga/2019 db/conf/fpga/fpga2019.html#LiuC19 Yi-Hsiang Lai Yuze Chi Yuwei Hu Jie Wang 0022 Cody Hao Yu Yuan Zhou Jason Cong Zhiru Zhang HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. 242-251 2019 FPGA https://doi.org/10.1145/3289602.3293910 https://www.wikidata.org/entity/Q130892128 conf/fpga/2019 db/conf/fpga/fpga2019.html#LaiCHWYZCZ19 Zhenyuan Ruan Tong He Jason Cong Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation Platform. 1-8 2019 ICCAD https://doi.org/10.1109/ICCAD45719.2019.8942135 conf/iccad/2019 db/conf/iccad/iccad2019.html#RuanHC19 Jiaxi Zhang 0001 Wentai Zhang 0001 Guojie Luo Xuechao Wei Yun Liang 0001 Jason Cong Frequency Improvement of Systolic Array-Based CNNs on FPGAs. 1-4 2019 ISCAS https://doi.org/10.1109/ISCAS.2019.8702071 conf/iscas/2019 db/conf/iscas/iscas2019.html#ZhangZLW0C19 Zhenyuan Ruan Tong He Jason Cong INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. 379-394 2019 USENIX ATC https://www.usenix.org/conference/atc19/presentation/ruan conf/usenix/2019 db/conf/usenix/usenix2019.html#RuanHC19 Ruipeng Gao Fan Ye 0003 Guojie Luo Jason Cong Smartphone-Based Indoor Map Construction - Principles and Applications Springer 2018 1-109 Springer Briefs in Computer Science 978-981-10-8377-8 https://doi.org/10.1007/978-981-10-8378-5

Jason Cong Zhenman Fang Muhuan Huang Libo Wang Di Wu 0010 CPU-FPGA Coscheduling for Big Data Applications. 16-22 2018 35 IEEE Des. Test 1 https://doi.org/10.1109/MDAT.2017.2741459 db/journals/dt/dt35.html#CongFHWW18

Cody Hao Yu Peng Wei 0004 Max Grossman Peng Zhang 0007 Vivek Sarkar Jason Cong S2FA: an accelerator automation framework for heterogeneous computing in datacenters. 153:1-153:6 2018 DAC https://doi.org/10.1145/3195970.3196109 https://doi.org/10.1109/DAC.2018.8465827 https://www.wikidata.org/entity/Q131121115 conf/dac/2018 db/conf/dac/dac2018.html#YuWGZSC18 Jason Cong Peng Wei 0004 Cody Hao Yu Peng Zhang 0007 Automated accelerator generation and optimization with composable, parallel and pipeline architecture. 154:1-154:6 2018 DAC https://doi.org/10.1145/3195970.3195999 https://doi.org/10.1109/DAC.2018.8465940 conf/dac/2018 db/conf/dac/dac2018.html#CongWYZ18 Zhenyuan Ruan Tong He Bojie Li Peipei Zhou 0001 Jason Cong ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. 9-16 2018 FCCM https://doi.org/10.1109/FCCM.2018.00011 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00011 conf/fccm/2018 db/conf/fccm/fccm2018.html#RuanHLZC18 Weikang Qiao Jieqiong Du Zhenman Fang Michael Lo Mau-Chung Frank Chang Jason Cong High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. 37-44 2018 FCCM https://doi.org/10.1109/FCCM.2018.00015 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00015 conf/fccm/2018 db/conf/fccm/fccm2018.html#QiaoDFLCC18 Jason Cong Zhenman Fang Michael Lo Hanrui Wang 0002 Jingxian Xu Shaochong Zhang Understanding Performance Differences of FPGAs and GPUs. 93-96 2018 FCCM https://doi.org/10.1109/FCCM.2018.00023 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00023 conf/fccm/2018 db/conf/fccm/fccm2018.html#CongFLWXZ18 Jason Cong Peng Wei 0004 Cody Hao Yu Peipei Zhou 0001 Latte: Locality Aware Transformation for High-Level Synthesis. 125-128 2018 FCCM https://doi.org/10.1109/FCCM.2018.00028 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00028 conf/fccm/2018 db/conf/fccm/fccm2018.html#CongWYZ18 Jason Cong Licheng Guo Po-Tsang Huang Peng Wei 0004 Tianhe Yu SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. 206 2018 FCCM https://doi.org/10.1109/FCCM.2018.00040 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00040 conf/fccm/2018 db/conf/fccm/fccm2018.html#CongGHWY18 Jason Cong Jie Wang 0022 Automatic Interior I/O Elimination in Systolic Array Architecture. 228 2018 FCCM https://doi.org/10.1109/FCCM.2018.00062 https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00062 conf/fccm/2018 db/conf/fccm/fccm2018.html#CongW18 Yuze Chi Peipei Zhou 0001 Jason Cong An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). 286 2018 FPGA https://doi.org/10.1145/3174243.3174964 conf/fpga/2018 db/conf/fpga/fpga2018.html#ChiZC18 Jason Cong Zhenman Fang Yao Hu Di Wu 0010 K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only). 287 2018 FPGA https://doi.org/10.1145/3174243.3174968 https://www.wikidata.org/entity/Q130851385 conf/fpga/2018 db/conf/fpga/fpga2018.html#CongFH018 Zhe Chen 0030 Andrew Howe Hugh T. Blair Jason Cong FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only). 288 2018 FPGA https://doi.org/10.1145/3174243.3174969 https://www.wikidata.org/entity/Q130853824 conf/fpga/2018 db/conf/fpga/fpga2018.html#ChenHBC18 Jason Cong Zhenman Fang Michael Lo Hanrui Wang 0002 Jingxian Xu Shaochong Zhang Understanding Performance Differences of FPGAs and GPUs: (Abtract Only). 288 2018 FPGA https://doi.org/10.1145/3174243.3174970 https://www.wikidata.org/entity/Q130857136 conf/fpga/2018 db/conf/fpga/fpga2018.html#CongFLWXZ18 Weikang Qiao Jieqiong Du Zhenman Fang Libo Wang Michael Lo Mau-Chung Frank Chang Jason Cong High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only). 291 2018 FPGA https://doi.org/10.1145/3174243.3174987 https://www.wikidata.org/entity/Q130849386 conf/fpga/2018 db/conf/fpga/fpga2018.html#QiaoDFWLCC18 Jason Cong Licheng Guo Po-Tsang Huang Peng Wei 0004 Tianhe Yu SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. 210-214 2018 FPL https://doi.org/10.1109/FPL.2018.00042 https://doi.ieeecomputersociety.org/10.1109/FPL.2018.00042 conf/fpl/2018 db/conf/fpl/fpl2018.html#CongGHWY18 Jason Cong Peng Wei 0004 Cody Hao Yu From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining. 2018 HotCloud https://www.usenix.org/conference/hotcloud18/presentation/cong conf/hotcloud/2018 db/conf/hotcloud/hotcloud2018.html#CongWY18 Peng Wang 0025 Shuo Li 0007 Guangyu Sun 0003 Xiaoyang Wang 0006 Yiran Chen 0001 Hai Li 0001 Jason Cong Nong Xiao 0001 Tao Zhang 0032 RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. 518-530 2018 HPCA https://doi.org/10.1109/HPCA.2018.00051 https://doi.ieeecomputersociety.org/10.1109/HPCA.2018.00051 conf/hpca/2018 db/conf/hpca/hpca2018.html#WangLSWCLCXZ18 Xuechao Wei Yun Liang 0001 Xiuhong Li Cody Hao Yu Peng Zhang 0007 Jason Cong TGPA: tile-grained pipeline architecture for low latency CNN inference. 58 2018 ICCAD https://doi.org/10.1145/3240765.3240856 https://ieeexplore.ieee.org/document/8587679/ conf/iccad/2018 db/conf/iccad/iccad2018.html#Wei0LYZC18 Young-kyu Choi Jason Cong HLS-based optimization and design space exploration for applications with variable loop bounds. 103 2018 ICCAD https://doi.org/10.1145/3240765.3240815 https://ieeexplore.ieee.org/document/8587738/ conf/iccad/2018 db/conf/iccad/iccad2018.html#ChoiC18 Yuze Chi Jason Cong Peng Wei 0004 Peipei Zhou 0001 SODA: stencil with optimized dataflow architecture. 116 2018 ICCAD https://doi.org/10.1145/3240765.3240850 https://ieeexplore.ieee.org/document/8587691/ conf/iccad/2018 db/conf/iccad/iccad2018.html#ChiCWZ18 Jason Cong Jie Wang 0022 PolySA: polyhedral-based systolic array auto-compilation. 117 2018 ICCAD https://doi.org/10.1145/3240765.3240838 https://ieeexplore.ieee.org/document/8587678/ conf/iccad/2018 db/conf/iccad/iccad2018.html#CongW18 Zhe Chen 0030 Andrew Howe Hugh T. Blair Jason Cong CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices. 2:1-2:6 2018 ISLPED https://doi.org/10.1145/3218603.3218637 conf/islped/2018 db/conf/islped/islped2018.html#ChenHBC18 Peipei Zhou 0001 Zhenyuan Ruan Zhenman Fang Megan Shand David Roazen Jason Cong Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework. 22-32 2018 ISPASS https://doi.org/10.1109/ISPASS.2018.00011 https://doi.ieeecomputersociety.org/10.1109/ISPASS.2018.00011 conf/ispass/2018 db/conf/ispass/ispass2018.html#ZhouRFSRC18 Yanghyo Kim Boyu Hu Yuan Du Adrian Tang 0002 Huan-Neng Ron Chen Chewnpu Jou Jason Cong Tatsuo Itoh Mau-Chung Frank Chang A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. 278-280 2018 ISSCC https://doi.org/10.1109/ISSCC.2018.8310292 conf/isscc/2018 db/conf/isscc/isscc2018.html#KimHD0CJCIC18 Meng Li 0016 Shiwen Shen Wen Gao 0001 William Hsu Jason Cong Computed Tomography Image Enhancement Using 3D Convolutional Neural Network. 291-299 2018 DLMIA/ML-CDS@MICCAI https://doi.org/10.1007/978-3-030-00889-5_33 conf/miccai/2018dlmia db/conf/miccai/dlmia2018.html#LiS0HC18 Jason Cong Joseph R. Shinnerl Large-Scale Global Placement. 2018 Handbook of Approximation Algorithms and Metaheuristics (2) books/tf/18/2018aam-2 db/books/collections/aam2018-2.html#CongS18

Jason Cong Zhenman Fang Yuchen Hao Peng Wei 0004 Cody Hao Yu Chen Zhang 0001 Peipei Zhou 0001 Best-Effort FPGA Programming: A Few Steps Can Go a Long Way. 2018 abs/1807.01340 CoRR http://arxiv.org/abs/1807.01340 db/journals/corr/corr1807.html#abs-1807-01340

Meng Li 0016 Shiwen Shen Wen Gao 0001 William Hsu Jason Cong Computed Tomography Image Enhancement using 3D Convolutional Neural Network. 2018 abs/1807.06821 CoRR http://arxiv.org/abs/1807.06821 db/journals/corr/corr1807.html#abs-1807-06821

Jason Cong Peng Wei 0004 Cody Hao Yu Peng Zhang 0007 AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture. 2018 abs/1809.07683 CoRR http://arxiv.org/abs/1809.07683 db/journals/corr/corr1809.html#abs-1809-07683

Yuze Chi Young-kyu Choi Jason Cong Jie Wang 0022 Rapid Cycle-Accurate Simulator for High-Level Synthesis. 2018 abs/1812.07012 CoRR http://arxiv.org/abs/1812.07012 db/journals/corr/corr1812.html#abs-1812-07012

Yijin Guan Ningyi Xu Chen Zhang 0001 Zhihang Yuan Jason Cong Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. 14-26 2017 APPT https://doi.org/10.1007/978-3-319-67952-5_2 conf/appt/2017 db/conf/appt/appt2017.html#GuanXZYC17 Xuechao Wei Yun Liang 0001 Tao Wang 0004 Songwu Lu Jason Cong Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. 488-493 2017 ASP-DAC https://doi.org/10.1109/ASPDAC.2017.7858370 conf/aspdac/2017 db/conf/aspdac/aspdac2017.html#WeiLWLC17 Yijin Guan Zhihang Yuan Guangyu Sun 0003 Jason Cong FPGA-based accelerator for long short-term memory recurrent neural networks. 629-634 2017 ASP-DAC https://doi.org/10.1109/ASPDAC.2017.7858394 conf/aspdac/2017 db/conf/aspdac/aspdac2017.html#GuanYSC17 Xuechao Wei Cody Hao Yu Peng Zhang 0007 Youxiang Chen Yuxin Wang Han Hu Yun Liang 0001 Jason Cong Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. 29:1-29:6 2017 DAC https://doi.org/10.1145/3061639.3062207 https://www.wikidata.org/entity/Q130968594 conf/dac/2017 db/conf/dac/dac2017.html#WeiYZCWHLC17 Jason Cong Peng Wei 0004 Cody Hao Yu Peipei Zhou 0001 Bandwidth Optimization Through On-Chip Memory Restructuring for HLS. 43:1-43:6 2017 DAC https://doi.org/10.1145/3061639.3062208 conf/dac/2017 db/conf/dac/dac2017.html#CongWYZ17 Young Kyu Choi Jason Cong HLScope: High-Level Performance Debugging for FPGA Designs. 125-128 2017 FCCM https://doi.org/10.1109/FCCM.2017.44 https://doi.ieeecomputersociety.org/10.1109/FCCM.2017.44 conf/fccm/2017 db/conf/fccm/fccm2017.html#ChoiC17 Yijin Guan Hao Liang 0003 Ningyi Xu Wenqiang Wang Shaoshuai Shi Xi Chen 0107 Guangyu Sun 0003 Wei Zhang 0012 Jason Cong FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. 152-159 2017 FCCM https://doi.org/10.1109/FCCM.2017.25 https://doi.ieeecomputersociety.org/10.1109/FCCM.2017.25 conf/fccm/2017 db/conf/fccm/fccm2017.html#GuanLXWSCSZC17 Jason Cong Zhenman Fang Muhuan Huang Libo Wang Di Wu 0010 CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). 291 2017 FPGA http://dl.acm.org/citation.cfm?id=3021787 conf/fpga/2017 db/conf/fpga/fpga2017.html#CongFHW017 Yuchen Hao Zhenman Fang Glenn Reinman Jason Cong Supporting Address Translation for Accelerator-Centric Architectures. 37-48 2017 HPCA https://doi.org/10.1109/HPCA.2017.19 https://doi.ieeecomputersociety.org/10.1109/HPCA.2017.19 conf/hpca/2017 db/conf/hpca/hpca2017.html#HaoFRC17 Meng Li 0016 Huizhu Jia Xiaodong Xie Jason Cong Wen Gao 0001 A cache-based bandwidth optimized motion compensation architecture for video decoder. 1303-1307 2017 ICASSP https://doi.org/10.1109/ICASSP.2017.7952367 conf/icassp/2017 db/conf/icassp/icassp2017.html#LiJXC017 Young-kyu Choi Peng Zhang 0007 Peng Li 0031 Jason Cong HLScope+, : Fast and accurate performance estimation for FPGA HLS. 691-698 2017 ICCAD https://doi.org/10.1109/ICCAD.2017.8203844 http://dl.acm.org/citation.cfm?id=3199792 conf/iccad/2017 db/conf/iccad/iccad2017.html#ChoiZLC17 Jason Cong Characterization and acceleration for genomic sequencing and analysis. 1 2017 IISWC https://doi.org/10.1109/IISWC.2017.8167744 https://doi.ieeecomputersociety.org/10.1109/IISWC.2017.8167744 conf/iiswc/2017 db/conf/iiswc/iiswc2017.html#Cong17 Jie Wang 0022 Xinfeng Xie Jason Cong Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. 72-81 2017 IPDPS https://doi.org/10.1109/IPDPS.2017.79 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2017.79 conf/ipps/2017 db/conf/ipps/ipdps2017.html#WangXC17 Jason Cong Zhenman Fang Michael Gill Farnoosh Javadi Glenn Reinman AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory. 3-14 2017 MEMSYS https://doi.org/10.1145/3132402.3132406 conf/memsys/2017 db/conf/memsys/memsys2017.html#CongFGJR17

Deming Chen Jason Cong Swathi T. Gurumani Wen-mei W. Hwu Kyle Rupnow Zhiru Zhang Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. 70-77 2016 1 IET Cyper-Phys. Syst.: Theory & Appl. 1 https://doi.org/10.1049/iet-cps.2016.0020 db/journals/iet-cps/iet-cps1.html#ChenCGHRZ16

Young Kyu Choi Jason Cong Acceleration of EM-Based 3D CT Reconstruction Using FPGA. 754-767 2016 10 IEEE Trans. Biomed. Circuits Syst. 3 https://doi.org/10.1109/TBCAS.2015.2471813 https://www.wikidata.org/entity/Q40437343 db/journals/tbcas/tbcas10.html#ChoiC16

Paolo Montuschi Edward J. McCluskey Samarjit Chakraborty Jason Cong Ramón M. Rodríguez-Dagnino Fred Douglis Lieven Eeckhout Gernot Heiser Sushil Jajodia Ruby B. Lee Dinesh Manocha Tomás F. Pena Isabelle Puaut Hanan Samet Donatella Sciuto State of the Journal. 2014-2018 2016 65 IEEE Trans. Computers 7 https://doi.org/10.1109/TC.2016.2568358 http://doi.ieeecomputersociety.org/10.1109/TC.2016.2568358 db/journals/tc/tc65.html#MontuschiMCCRDE16

Jason Cong Peng Li 0031 Bingjun Xiao Peng Zhang 0007 An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. 407-418 2016 35 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2015.2488491 db/journals/tcad/tcad35.html#CongLXZ16

Alberto A. Del Barrio Jason Cong Román Hermida A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. 419-432 2016 35 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2015.2474362 db/journals/tcad/tcad35.html#BarrioCH16

Ying Chen Tan Nguyen Yao Chen 0008 Swathi T. Gurumani Yun Liang 0001 Kyle Rupnow Jason Cong Wen-mei W. Hwu Deming Chen FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. 2032-2045 2016 35 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2016.2552821 db/journals/tcad/tcad35.html#ChenNCGLRCHC16

Jason Cong Hui Huang 0001 Mohammad Ali Ghodrat A scalable communication-aware compilation flow for programmable accelerators. 503-510 2016 ASP-DAC https://doi.org/10.1109/ASPDAC.2016.7428062 conf/aspdac/2016 db/conf/aspdac/aspdac2016.html#Cong0G16 Muhuan Huang Di Wu 0010 Cody Hao Yu Zhenman Fang Matteo Interlandi Tyson Condie Jason Cong Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale. 456-469 2016 SoCC https://doi.org/10.1145/2987550.2987569 https://www.wikidata.org/entity/Q87605997 conf/cloud/2016 db/conf/cloud/socc2016.html#HuangWYFICC16 Jason Cong Muhuan Huang Di Wu 0010 Cody Hao Yu Invited - Heterogeneous datacenters: options and opportunities. 16:1-16:6 2016 DAC https://doi.org/10.1145/2897937.2905012 conf/dac/2016 db/conf/dac/dac2016.html#CongHWY16 Young-kyu Choi Jason Cong Zhenman Fang Yuchen Hao Glenn Reinman Peng Wei 0004 A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. 109:1-109:6 2016 DAC https://doi.org/10.1145/2897937.2897972 https://www.wikidata.org/entity/Q130877660 conf/dac/2016 db/conf/dac/dac2016.html#ChoiCFHRW16 Yu-Ting Chen 0003 Jason Cong Zhenman Fang Jie Lei 0001 Peng Wei 0004 When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. 29 2016 FCCM https://doi.org/10.1109/FCCM.2016.18 https://doi.ieeecomputersociety.org/10.1109/FCCM.2016.18 conf/fccm/2016 db/conf/fccm/fccm2016.html#ChenCFLW16 Mau-Chung Frank Chang Yu-Ting Chen 0003 Jason Cong Po-Tsang Huang Chun-Liang Kuo Cody Hao Yu The SMEM Seeding Acceleration for DNA Sequence Alignment. 32-39 2016 FCCM https://doi.org/10.1109/FCCM.2016.21 https://doi.ieeecomputersociety.org/10.1109/FCCM.2016.21 https://www.wikidata.org/entity/Q59616159 conf/fccm/2016 db/conf/fccm/fccm2016.html#ChangCCHKY16 Peipei Zhou 0001 Hyunseok Park Zhenman Fang Jason Cong André DeHon Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. 172-175 2016 FCCM https://doi.org/10.1109/FCCM.2016.50 https://doi.ieeecomputersociety.org/10.1109/FCCM.2016.50 conf/fccm/2016 db/conf/fccm/fccm2016.html#ZhouPFCD16 Jie Lei 0001 Yu-Ting Chen 0003 Yunsong Li 0001 Jason Cong A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). 277 2016 FPGA https://doi.org/10.1145/2847263.2847305 https://www.wikidata.org/entity/Q130849376 conf/fpga/2016 db/conf/fpga/fpga2016.html#LeiCLC16 Yu-Ting Chen 0003 Jason Cong Zhenman Fang Peipei Zhou 0001 ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). 281 2016 FPGA https://doi.org/10.1145/2847263.2847302 conf/fpga/2016 db/conf/fpga/fpga2016.html#ChenCFZ16 Yu-Ting Chen 0003 Jason Cong Zhenman Fang Jie Lei 0001 Peng Wei 0004 When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. 2016 HotCloud https://www.usenix.org/conference/hotcloud16/workshop-program/presentation/chen conf/hotcloud/2016 db/conf/hotcloud/hotcloud2016.html#ChenCFLW16 Chen Zhang 0001 Zhenman Fang Peipei Zhou 0001 Peichen Pan Jason Cong Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. 12:1-12:8 2016 ICCAD https://doi.org/10.1145/2966986.2967011 conf/iccad/2016 db/conf/iccad/iccad2016.html#ZhangFZPC16 Jason Cong Muhuan Huang Peichen Pan Di Wu 0010 Peng Zhang 0007 Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper. 154-155 2016 ISLPED https://doi.org/10.1145/2934583.2953984 https://www.wikidata.org/entity/Q130867393 conf/islped/2016 db/conf/islped/islped2016.html#CongHPWZ16 Chen Zhang 0001 Di Wu 0010 Jiayu Sun Guangyu Sun 0003 Guojie Luo Jason Cong Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. 326-331 2016 ISLPED https://doi.org/10.1145/2934583.2934644 https://www.wikidata.org/entity/Q130872583 conf/islped/2016 db/conf/islped/islped2016.html#ZhangWSSLC16 Guojie Luo Wentai Zhang 0001 Jiaxi Zhang 0001 Jason Cong Scaling Up Physical Design: Challenges and Opportunities. 131-137 2016 ISPD https://doi.org/10.1145/2872334.2872342 https://www.wikidata.org/entity/Q131116124 conf/ispd/2016 db/conf/ispd/ispd2016.html#LuoZZC16 Jason Cong Muhuan Huang Peichen Pan Yuxin Wang Peng Zhang 0007 Source-to-Source Optimization for HLS. 137-163 2016 FPGAs for Software Programmers https://doi.org/10.1007/978-3-319-26408-0_8 books/daglib/0040430 db/books/collections/KHZ2016.html#CongHPW016 Jason Cong Yuzheng Ding FPGA Technology Mapping. 773-777 2016 Encyclopedia of Algorithms https://doi.org/10.1007/978-1-4939-2864-4_148 db/reference/algo/algo2016.html#CongD16

Yu-Ting Chen 0003 Jason Cong Zhenman Fang Bingjun Xiao Peipei Zhou 0001 ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. 2016 abs/1610.09761 CoRR http://arxiv.org/abs/1610.09761 db/journals/corr/corr1610.html#ChenCFXZ16

Jason Cong Zhenman Fang Hassan Kianinejad Peng Wei 0004 Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis. 2016 abs/1611.04474 CoRR http://arxiv.org/abs/1611.04474 db/journals/corr/corr1611.html#CongFKW16

Yu-Ting Chen 0003 Jason Cong Michael Gill Glenn Reinman Bingjun Xiao Customizable Computing Morgan & Claypool Publishers 2015 Synthesis Lectures on Computer Architecture 978-3-031-00620-3 978-3-031-01748-3 https://doi.org/10.2200/S00650ED1V01Y201505CAC033 https://doi.org/10.1007/978-3-031-01748-3

Shiwen Shen Alex A. T. Bui Jason Cong William Hsu An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy. 139-149 2015 57 Comput. Biol. Medicine https://doi.org/10.1016/j.compbiomed.2014.12.008 https://www.wikidata.org/entity/Q46860331 db/journals/cbm/cbm57.html#ShenBCH15

Peng Wang 0025 Le Cao Chunbo Lai Leqi Zou Guangyu Sun 0003 Jason Cong InterFS: An Interplanted Distributed File System to Improve Storage Utilization. 14:1-14:8 2015 APSys https://doi.org/10.1145/2797022.2797036 https://www.wikidata.org/entity/Q131013705 conf/apsys/2015 db/conf/apsys/apsys2015.html#WangCLZSC15 Jason Cong Michael Gill Yuchen Hao Glenn Reinman Bo Yuan On-chip interconnection network for accelerator-rich architectures. 8:1-8:6 2015 DAC https://doi.org/10.1145/2744769.2744879 conf/dac/2015 db/conf/dac/dac2015.html#CongGHRY15 Peng Zhang 0007 Muhuan Huang Bingjun Xiao Hui Huang 0001 Jason Cong CMOST: a system-level FPGA compilation framework. 158:1-158:6 2015 DAC https://doi.org/10.1145/2744769.2744807 https://www.wikidata.org/entity/Q130887406 conf/dac/2015 db/conf/dac/dac2015.html#ZhangHXHC15 Yu-Ting Chen 0003 Jason Cong Jie Lei 0001 Peng Wei 0004 A Novel High-Throughput Acceleration Engine for Read Alignment. 199-202 2015 FCCM https://doi.org/10.1109/FCCM.2015.27 https://doi.ieeecomputersociety.org/10.1109/FCCM.2015.27 conf/fccm/2015 db/conf/fccm/fccm2015.html#ChenCLW15 John Lockwood Michael Adler Dan Mansur Derek Chiou Mike Strickland Jason Cong Steve Teig Growing a Healthy FPGA Ecosystem. 160 2015 FPGA https://doi.org/10.1145/2684746.2721404 https://www.wikidata.org/entity/Q130863003 conf/fpga/2015 db/conf/fpga/fpga2015.html#LockwoodAMCSCT15 Chen Zhang 0001 Peng Li 0031 Guangyu Sun 0003 Yijin Guan Bingjun Xiao Jason Cong Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. 161-170 2015 FPGA https://doi.org/10.1145/2684746.2689060 conf/fpga/2015 db/conf/fpga/fpga2015.html#ZhangLSGXC15 Peng Li 0031 Peng Zhang 0007 Louis-Noël Pouchet Jason Cong Resource-Aware Throughput Optimization for High-Level Synthesis. 200-209 2015 FPGA https://doi.org/10.1145/2684746.2689065 conf/fpga/2015 db/conf/fpga/fpga2015.html#LiZPC15 Wentai Zhang 0001 Li Shen Thomas Page Guojie Luo Peng Li 0031 Peter Maaß Ming Jiang 0001 Jason Cong FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). 261 2015 FPGA https://doi.org/10.1145/2684746.2689097 https://www.wikidata.org/entity/Q130867366 conf/fpga/2015 db/conf/fpga/fpga2015.html#ZhangSPLLMJC15 Jie Wang 0022 Jason Cong Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). 276 2015 FPGA https://doi.org/10.1145/2684746.2689147 https://www.wikidata.org/entity/Q130866278 conf/fpga/2015 db/conf/fpga/fpga2015.html#WangC15 Jason Cong Cody Hao Yu Impact of Loop Transformations on Software Reliability. 278-285 2015 ICCAD https://doi.org/10.1109/ICCAD.2015.7372581 http://dl.acm.org/citation.cfm?id=2840859 conf/iccad/2015 db/conf/iccad/iccad2015.html#CongY15 Jason Cong Zhenman Fang Michael Gill Glenn Reinman PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration. 380-387 2015 ICCAD https://doi.org/10.1109/ICCAD.2015.7372595 http://dl.acm.org/citation.cfm?id=2840873 conf/iccad/2015 db/conf/iccad/iccad2015.html#CongFGR15 Meng Li 0016 Peng Zhang 0007 Chuang Zhu Huizhu Jia Xiaodong Xie Jason Cong Wen Gao 0001 High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis. 92-95 2015 ICCE https://doi.org/10.1109/ICCE.2015.7066333 conf/iccel/2015 db/conf/iccel/icce2015.html#LiZZJXC015 Yu-Ting Chen 0003 Jason Cong Interconnect synthesis of heterogeneous accelerators in a shared memory architecture. 359-364 2015 ISLPED https://doi.org/10.1109/ISLPED.2015.7273540 conf/islped/2015 db/conf/islped/islped2015.html#ChenC15 Yu-Ting Chen 0003 Jason Cong Bingjun Xiao ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. 157-158 2015 ISPASS https://doi.org/10.1109/ISPASS.2015.7095795 https://doi.ieeecomputersociety.org/10.1109/ISPASS.2015.7095795 conf/ispass/2015 db/conf/ispass/ispass2015.html#ChenCX15 Chunbo Lai Song Jiang 0001 Liqiong Yang Shiding Lin Guangyu Sun 0003 Zhenyu Hou Can Cui Jason Cong Atlas: Baidu's key-value storage system for cloud data. 1-14 2015 MSST https://doi.org/10.1109/MSST.2015.7208288 https://doi.ieeecomputersociety.org/10.1109/MSST.2015.7208288 conf/mss/2015 db/conf/mss/msst2015.html#LaiJYLSHCC15 Jason Cong "High-level synthesis and beyond - From datacenters to IoTs". 2015 SoCC https://doi.org/10.1109/SOCC.2015.7406893 conf/socc/2015 db/conf/socc/socc2015.html#Cong15

Jason Cong Henry Duwe Rakesh Kumar 0002 Sen Li Better-Than-Worst-Case Design: Progress and Opportunities. 656-663 2014 29 J. Comput. Sci. Technol. 4 https://doi.org/10.1007/s11390-014-1457-2 db/journals/jcst/jcst29.html#CongDKL14

Tao Wang 0004 Guangyu Sun 0003 Jiahua Chen Jian Gong Haoyang Wu Xiaoguang Li Songwu Lu Jason Cong GRT: A Reconfigurable SDR Platform with High Performance and Usability. 51-56 2014 42 SIGARCH Comput. Archit. News 4 https://doi.org/10.1145/2693714.2693724 db/journals/sigarch/sigarch42.html#WangSCGWLLC14

Jason Cong Mohammad Ali Ghodrat Michael Gill Beayna Grigorian Glenn Reinman Architecture Support for Domain-Specific Accelerator-Rich CMPs. 131:1-131:26 2014 13 ACM Trans. Embed. Comput. Syst. 4s https://doi.org/10.1145/2584664 db/journals/tecs/tecs13.html#CongGGGR14

Anpeng Huang Wenyao Xu Zhinan Li Linzhen Xie Majid Sarrafzadeh Xiaoming Li 0001 Jason Cong System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project. 1581-1589 2014 18 IEEE J. Biomed. Health Informatics 5 https://doi.org/10.1109/JBHI.2013.2292576 https://www.wikidata.org/entity/Q30847786 db/journals/titb/titb18.html#HuangXLXSLC14

Jason Cong Bingjun Xiao FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. 864-877 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2013.2259512 db/journals/tvlsi/tvlsi22.html#CongX14

Jason Cong Peng Li 0031 Bingjun Xiao Peng Zhang 0007 An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. 77:1-77:6 2014 DAC https://doi.org/10.1145/2593069.2593090 conf/dac/2014 db/conf/dac/dac2014.html#CongLXZ14 Jason Cong Mohammad Ali Ghodrat Michael Gill Beayna Grigorian Karthik Gururaj Glenn Reinman Accelerator-Rich Architectures: Opportunities and Progresses. 180:1-180:6 2014 DAC https://doi.org/10.1145/2593069.2596667 conf/dac/2014 db/conf/dac/dac2014.html#CongGGGGR14 Peng Wang 0025 Guangyu Sun 0003 Song Jiang 0001 Jian Ouyang Shiding Lin Chen Zhang 0001 Jason Cong An efficient design and implementation of LSM-tree based key-value store on open-channel SSD. 16:1-16:14 2014 EuroSys https://doi.org/10.1145/2592798.2592804 https://www.wikidata.org/entity/Q130954040 conf/eurosys/2014 db/conf/eurosys/eurosys2014.html#WangSJOLZC14 Jason Cong Hui Huang 0001 Chiyuan Ma Bingjun Xiao Peipei Zhou 0001 A Fully Pipelined and Dynamically Composable Architecture of CGRA. 9-16 2014 FCCM https://doi.org/10.1109/FCCM.2014.12 https://doi.ieeecomputersociety.org/10.1109/FCCM.2014.12 conf/fccm/2014 db/conf/fccm/fccm2014.html#Cong0MXZ14 Young Kyu Choi Jason Cong Di Wu 0010 FPGA Implementation of EM Algorithm for 3D CT Reconstruction. 157-160 2014 FCCM https://doi.org/10.1109/FCCM.2014.48 https://doi.ieeecomputersociety.org/10.1109/FCCM.2014.48 conf/fccm/2014 db/conf/fccm/fccm2014.html#ChoiCW14 Peng Li 0031 Thomas Page Guojie Luo Wentai Zhang 0001 Pei Wang Peng Zhang 0007 Peter Maass Ming Jiang 0001 Jason Cong FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. 172 2014 FCCM https://doi.org/10.1109/FCCM.2014.54 https://doi.ieeecomputersociety.org/10.1109/FCCM.2014.54 conf/fccm/2014 db/conf/fccm/fccm2014.html#LiPLZWZMJC14 Yuxin Wang Peng Li 0031 Jason Cong Theory and algorithm for generalized memory partitioning in high-level synthesis. 199-208 2014 FPGA https://doi.org/10.1145/2554688.2554780 conf/fpga/2014 db/conf/fpga/fpga2014.html#WangLC14 Jason Cong Muhuan Huang Peng Zhang 0007 Combining computation and communication optimizations in system synthesis for streaming applications. 213-222 2014 FPGA https://doi.org/10.1145/2554688.2554771 conf/fpga/2014 db/conf/fpga/fpga2014.html#CongHZ14 Peng Li 0031 Louis-Noël Pouchet Deming Chen Jason Cong Transformations for throughput optimization in high-level synthesis (abstract only). 245 2014 FPGA https://doi.org/10.1145/2554688.2554772 conf/fpga/2014 db/conf/fpga/fpga2014.html#LiPCC14 Jian Gong Jiahua Chen Haoyang Wu Fan Ye 0003 Songwu Lu Jason Cong Tao Wang 0004 EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only). 255 2014 FPGA https://doi.org/10.1145/2554688.2554723 conf/fpga/2014 db/conf/fpga/fpga2014.html#GongCWYLCW14 Jian Gong Tao Wang 0004 Jiahua Chen Haoyang Wu Fan Ye 0003 Songwu Lu Jason Cong An efficient and flexible host-FPGA PCIe communication library. 1-6 2014 FPL https://doi.org/10.1109/FPL.2014.6927459 conf/fpl/2014 db/conf/fpl/fpl2014.html#GongWCWYLC14 Muhuan Huang Kevin Lim Jason Cong A scalable, high-performance customized priority queue. 1-4 2014 FPL https://doi.org/10.1109/FPL.2014.6927413 conf/fpl/2014 db/conf/fpl/fpl2014.html#HuangLC14 Jason Cong Automating customized computing. 2 2014 FPT https://doi.org/10.1109/FPT.2014.7082743 conf/fpt/2014 db/conf/fpt/fpt2014.html#Cong14 Jason Cong Bingjun Xiao Minimizing Computation in Convolutional Neural Networks. 281-290 2014 ICANN https://doi.org/10.1007/978-3-319-11179-7_36 conf/icann/2014 db/conf/icann/icann2014.html#CongX14 Jason Cong Accelerator-rich architectures: from single-chip to datacenters. 139-140 2014 ISLPED https://doi.org/10.1145/2627369.2631636 https://www.wikidata.org/entity/Q131125186 conf/islped/2014 db/conf/islped/islped2014.html#Cong14 Jason Cong From design to design automation. 121-126 2014 ISPD https://doi.org/10.1145/2560519.2568052 conf/ispd/2014 db/conf/ispd/ispd2014.html#Cong14

Chunhua Xiao M.-C. Frank Chang Jason Cong Michael Gill Zhangqin Huang Chunyue Liu Glenn Reinman Hao Wu 0026 Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects. 60:1-60:27 2013 9 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2400682.2400719 https://www.wikidata.org/entity/Q59616583 db/journals/taco/taco9.html#XiaoCCGHLRW13

Guojie Luo Yiyu Shi 0001 Jason Cong An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. 510-523 2013 32 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2012.2232708 db/journals/tcad/tcad32.html#LuoSC13

Alexandros Papakonstantinou Karthik Gururaj John A. Stratton Deming Chen Jason Cong Wen-mei W. Hwu Efficient compilation of CUDA kernels for high-performance computing on FPGAs. 25:1-25:26 2013 13 ACM Trans. Embed. Comput. Syst. 2 https://doi.org/10.1145/2514641.2514652 https://www.wikidata.org/entity/Q131113600 db/journals/tecs/tecs13.html#PapakonstantinouGSCCH13

Amit Agarwal Jason Cong Brian Tagiku The survivability of design-specific spare placement in FPGA architectures with high defect rates. 33:1-33:22 2013 18 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/2442087.2442104 https://www.wikidata.org/entity/Q130876055 db/journals/todaes/todaes18.html#AgarwalCT13

Jason Cong Guojie Luo Kalliopi Tsota Bingjun Xiao Optimizing routability in large-scale mixed-size placement. 441-446 2013 ASP-DAC https://doi.org/10.1109/ASPDAC.2013.6509636 conf/aspdac/2013 db/conf/aspdac/aspdac2013.html#CongLTX13 Wei Zuo Peng Li 0031 Deming Chen Louis-Noël Pouchet Shunan Zhong Jason Cong Improving polyhedral code generation for high-level synthesis. 15:1-15:10 2013 CODES+ISSS https://doi.org/10.1109/CODES-ISSS.2013.6659002 http://dl.acm.org/citation.cfm?id=2555707 conf/codes/2013 db/conf/codes/codes2013.html#ZuoLCPZC13 Jason Cong Bingjun Xiao Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. 9:1-9:8 2013 DAC https://doi.org/10.1145/2463209.2488745 conf/dac/2013 db/conf/dac/dac2013.html#CongX13 Alexandros Papakonstantinou Deming Chen Wen-mei W. Hwu Jason Cong Yun Liang 0001 Throughput-oriented kernel porting onto FPGAs. 11:1-11:10 2013 DAC https://doi.org/10.1145/2463209.2488747 conf/dac/2013 db/conf/dac/dac2013.html#PapakonstantinouCHCL13 Yuxin Wang Peng Li 0031 Peng Zhang 0007 Chen Zhang 0001 Jason Cong Memory partitioning for multidimensional arrays in high-level synthesis. 12:1-12:8 2013 DAC https://doi.org/10.1145/2463209.2488748 conf/dac/2013 db/conf/dac/dac2013.html#WangLZZC13 Jason Cong Hugh T. Blair Di Wu 0010 FPGA Simulation Engine for Customized Construction of Neural Microcircuit. 229 2013 FCCM https://doi.org/10.1109/FCCM.2013.22 https://doi.ieeecomputersociety.org/10.1109/FCCM.2013.22 https://www.wikidata.org/entity/Q41589367 conf/fccm/2013 db/conf/fccm/fccm2013.html#CongBW13 Wei Zuo Yun Liang 0001 Peng Li 0031 Kyle Rupnow Deming Chen Jason Cong Improving high level synthesis optimization opportunity through polyhedral transformations. 9-18 2013 FPGA https://doi.org/10.1145/2435264.2435271 conf/fpga/2013 db/conf/fpga/fpga2013.html#ZuoLLRCC13 Louis-Noël Pouchet Peng Zhang 0007 P. Sadayappan Jason Cong Polyhedral-based data reuse optimization for configurable computing. 29-38 2013 FPGA https://doi.org/10.1145/2435264.2435273 conf/fpga/2013 db/conf/fpga/fpga2013.html#PouchetZSC13 Vaughn Betz Jason Cong Are FPGAs suffering from the innovator's dilemna? 135-136 2013 FPGA https://doi.org/10.1145/2435264.2435289 conf/fpga/2013 db/conf/fpga/fpga2013.html#BetzC13 Jason Cong Karthik Gururaj Architecture support for custom instructions with memory operations. 231-234 2013 FPGA https://doi.org/10.1145/2435264.2435303 conf/fpga/2013 db/conf/fpga/fpga2013.html#CongG13 Yuxin Wang Peng Li 0031 Peng Zhang 0007 Chen Zhang 0001 Jason Cong Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). 269 2013 FPGA https://doi.org/10.1145/2435264.2435321 https://www.wikidata.org/entity/Q130877668 conf/fpga/2013 db/conf/fpga/fpga2013.html#WangLZZC13 Jason Cong Muhuan Huang Peng Zhang 0007 Efficient system-level mapping from streaming applications to FPGAs (abstract only). 277 2013 FPGA https://doi.org/10.1145/2435264.2435342 conf/fpga/2013 db/conf/fpga/fpga2013.html#CongHZ13 Jason Cong Bingjun Xiao Defect recovery in nanodevice-based programmable interconnects (abstract only). 277-278 2013 FPGA https://doi.org/10.1145/2435264.2435343 conf/fpga/2013 db/conf/fpga/fpga2013.html#CongX13 Hugh T. Blair Jason Cong Di Wu 0010 FPGA simulation engine for customized construction of neural microcircuits. 607-614 2013 ICCAD https://doi.org/10.1109/ICCAD.2013.6691179 http://dl.acm.org/citation.cfm?id=2561949 conf/iccad/2013 db/conf/iccad/iccad2013.html#BlairCW13 Jason Cong Bingjun Xiao Optimization of interconnects between accelerators and shared memories in dark silicon. 630-637 2013 ICCAD https://doi.org/10.1109/ICCAD.2013.6691182 http://dl.acm.org/citation.cfm?id=2561953 conf/iccad/2013 db/conf/iccad/iccad2013.html#CongX13 Yu-Ting Chen 0003 Jason Cong Mohammad Ali Ghodrat Muhuan Huang Chunyue Liu Bingjun Xiao Yi Zou Accelerator-rich CMPs: From concept to real hardware. 169-176 2013 ICCD https://doi.org/10.1109/ICCD.2013.6657039 https://doi.ieeecomputersociety.org/10.1109/ICCD.2013.6657039 conf/iccd/2013 db/conf/iccd/iccd2013.html#ChenCGHLXZ13 Peng Wang 0025 Guangyu Sun 0003 Tao Wang 0004 Yuan Xie 0001 Jason Cong Designing scratchpad memory architecture with emerging STT-RAM memory technologies. 1244-1247 2013 ISCAS https://doi.org/10.1109/ISCAS.2013.6572078 conf/iscas/2013 db/conf/iscas/iscas2013.html#WangSWXC13 Jason Cong Milos D. Ercegovac Muhuan Huang Sen Li Bingjun Xiao Energy-efficient computing using adaptive table lookup based on nonvolatile memories. 280-285 2013 ISLPED https://doi.org/10.1109/ISLPED.2013.6629309 http://dl.acm.org/citation.cfm?id=2648738 conf/islped/2013 db/conf/islped/islped2013.html#CongEHLX13 Jason Cong Mohammad Ali Ghodrat Michael Gill Beayna Grigorian Hui Huang 0001 Glenn Reinman Composable accelerator-rich microprocessor enhanced for adaptivity and longevity. 305-310 2013 ISLPED https://doi.org/10.1109/ISLPED.2013.6629314 http://dl.acm.org/citation.cfm?id=2648744 conf/islped/2013 db/conf/islped/islped2013.html#CongGGG0R13

Yanghyo Kim Sai-Wang Tam Gyungsu Byun Hao Wu 0026 Lan Nan Glenn Reinman Jason Cong Mau-Chung Frank Chang Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. 200-209 2012 2 IEEE J. Emerg. Sel. Topics Circuits Syst. 2 https://doi.org/10.1109/JETCAS.2012.2193511 https://www.wikidata.org/entity/Q59616486 db/journals/esticas/esticas2.html#KimTBWNRCC12

Kanit Therdsteerasukdi Gyungsu Byun Jeremy Ir Glenn Reinman Jason Cong Mau-Chung Frank Chang Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. 210-227 2012 2 IEEE J. Emerg. Sel. Topics Circuits Syst. 2 https://doi.org/10.1109/JETCAS.2012.2193843 https://www.wikidata.org/entity/Q59616603 db/journals/esticas/esticas2.html#TherdsteerasukdiBIRCC12

Jianwen Chen Jason Cong Luminita A. Vese John D. Villasenor Ming Yan 0006 Yi Zou A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. 616-625 2012 2 IEEE J. Emerg. Sel. Topics Circuits Syst. 3 https://doi.org/10.1109/JETCAS.2012.2221530 db/journals/esticas/esticas2.html#ChenCVVYZ12

Jason Cong Karthik Gururaj Peng Zhang 0007 Yi Zou Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. 2012 2012 J. Electr. Comput. Eng. https://doi.org/10.1155/2012/691864 https://www.wikidata.org/entity/Q58908642 db/journals/jece/jece2012.html#CongGZZ12 691864:1-691864:24

Kanit Therdsteerasukdi Gyungsu Byun Jason Cong M. Frank Chang Glenn Reinman Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. 51:1-51:19 2012 8 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2086696.2086730 db/journals/taco/taco8.html#TherdsteerasukdiBCCR12

Alex A. T. Bui Kwang-Ting Cheng Jason Cong Luminita A. Vese Yi-Chu Wang Bo Yuan Yi Zou Platform characterization for Domain-Specific Computing. 94-99 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6165071 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#BuiCCVWYZ12 Yuxin Wang Peng Zhang 0007 Xu Cheng 0001 Jason Cong An integrated and automated memory optimization flow for FPGA behavioral synthesis. 257-262 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6164955 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#WangZCC12 Jason Cong Mohammad Ali Ghodrat Michael Gill Hui Huang 0001 Bin Liu 0006 Raghu Prabhakar Glenn Reinman Marco Vitanza Compilation and architecture support for customized vector instruction extension. 652-657 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6165037 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#CongGGHLPRV12 Hao Wu 0026 Lan Nan Sai-Wang Tam Hsieh-Hung Hsieh Chewnpu Jou Glenn Reinman Jason Cong Mau-Chung Frank Chang A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. 1-4 2012 CICC https://doi.org/10.1109/CICC.2012.6330666 https://www.wikidata.org/entity/Q59616200 conf/cicc/2012 db/conf/cicc/cicc2012.html#WuNTHJRCC12 Jason Cong Mohammad Ali Ghodrat Michael Gill Beayna Grigorian Glenn Reinman Architecture support for accelerator-rich CMPs. 843-849 2012 DAC https://doi.org/10.1145/2228360.2228512 conf/dac/2012 db/conf/dac/dac2012.html#CongGGGR12 Jason Cong Peng Zhang 0007 Yi Zou Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. 1233-1238 2012 DAC https://doi.org/10.1145/2228360.2228586 conf/dac/2012 db/conf/dac/dac2012.html#CongZZ12 Jason Cong Bin Liu 0006 A metric for layout-friendly microarchitecture optimization in high-level synthesis. 1239-1244 2012 DAC https://doi.org/10.1145/2228360.2228587 conf/dac/2012 db/conf/dac/dac2012.html#CongL12 Yu-Ting Chen 0003 Jason Cong Hui Huang 0001 Bin Liu 0006 Chunyue Liu Miodrag Potkonjak Glenn Reinman Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. 45-50 2012 DATE https://doi.org/10.1109/DATE.2012.6176431 https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176431 http://dl.acm.org/citation.cfm?id=2492721 conf/date/2012 db/conf/date/date2012.html#ChenCHLLPR12 Jason Cong Muhuan Huang Bin Liu 0006 Peng Zhang 0007 Yi Zou Combining module selection and replication for throughput-driven streaming programs. 1018-1023 2012 DATE https://doi.org/10.1109/DATE.2012.6176645 https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176645 http://dl.acm.org/citation.cfm?id=2492962 conf/date/2012 db/conf/date/date2012.html#CongHLZZ12 Jianwen Chen Jason Cong Ming Yan 0006 Yi Zou FPGA-accelerated 3D reconstruction using compressive sensing. 163-166 2012 FPGA https://doi.org/10.1145/2145694.2145721 https://www.wikidata.org/entity/Q130857141 conf/fpga/2012 db/conf/fpga/fpga2012.html#ChenCYZ12 Jason Cong Bingjun Xiao FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). 268 2012 FPGA https://doi.org/10.1145/2145694.2145751 https://www.wikidata.org/entity/Q130855598 conf/fpga/2012 db/conf/fpga/fpga2012.html#CongX12 Peng Li 0031 Yuxin Wang Peng Zhang 0007 Guojie Luo Tao Wang 0004 Jason Cong Memory partitioning and scheduling co-optimization in behavioral synthesis. 488-495 2012 ICCAD https://doi.org/10.1145/2429384.2429484 https://ieeexplore.ieee.org/document/6386711/ conf/iccad/2012 db/conf/iccad/iccad2012.html#LiWZLWC12 Jason Cong Mohammad Ali Ghodrat Michael Gill Chunyue Liu Glenn Reinman BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. 225-230 2012 ISLPED https://doi.org/10.1145/2333660.2333715 conf/islped/2012 db/conf/islped/islped2012.html#CongGGLR12 Yu-Ting Chen 0003 Jason Cong Hui Huang 0001 Chunyue Liu Raghu Prabhakar Glenn Reinman Static and dynamic co-optimizations for blocks mapping in hybrid caches. 237-242 2012 ISLPED https://doi.org/10.1145/2333660.2333717 conf/islped/2012 db/conf/islped/islped2012.html#ChenCHLPR12 Jason Cong Bo Yuan Energy-efficient scheduling on heterogeneous multi-core architectures. 345-350 2012 ISLPED https://doi.org/10.1145/2333660.2333737 conf/islped/2012 db/conf/islped/islped2012.html#CongY12 Jason Cong Mohammad Ali Ghodrat Michael Gill Beayna Grigorian Glenn Reinman CHARM: a composable heterogeneous accelerator-rich microprocessor. 379-384 2012 ISLPED https://doi.org/10.1145/2333660.2333747 https://www.wikidata.org/entity/Q130951338 conf/islped/2012 db/conf/islped/islped2012.html#CongGGGR12 Jason Cong Transformation from ad hoc EDA to algorithmic EDA. 57-62 2012 ISPD https://doi.org/10.1145/2160916.2160929 conf/ispd/2012 db/conf/ispd/ispd2012.html#Cong12 Jason Cong Bin Liu 0006 Guojie Luo Raghu Prabhakar Towards layout-friendly high-level synthesis. 165-172 2012 ISPD https://doi.org/10.1145/2160916.2160952 conf/ispd/2012 db/conf/ispd/ispd2012.html#CongLLP12 Kan Wang 0003 Sheqin Dong Yuchun Ma Satoshi Goto Jason Cong Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. 129-136 2012 ISQED https://doi.org/10.1109/ISQED.2012.6187485 conf/isqed/2012 db/conf/isqed/isqed2012.html#WangDMGC12 Yanghyo Kim Gyungsu Byun Adrian Tang 0002 Chewnpu Jou Hsieh-Hung Hsieh Glenn Reinman Jason Cong Mau-Chung Frank Chang An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. 50-52 2012 ISSCC https://doi.org/10.1109/ISSCC.2012.6176874 https://www.wikidata.org/entity/Q59616212 conf/isscc/2012 db/conf/isscc/isscc2012.html#KimBTJHRCC12 Jason Cong Bin Liu 0006 Raghu Prabhakar Peng Zhang 0007 A Study on the Impact of Compiler Optimizations on High-Level Synthesis. 143-157 2012 LCPC https://doi.org/10.1007/978-3-642-37658-0_10 conf/lcpc/2012 db/conf/lcpc/lcpc2012.html#CongLPZ12 Alina Simion Sbîrlea Yi Zou Zoran Budimlic Jason Cong Vivek Sarkar Mapping a data-flow programming model onto heterogeneous platforms. 61-70 2012 LCTES https://doi.org/10.1145/2248418.2248428 https://doi.org/10.1145/2345141.2248428 conf/lctrts/2012 db/conf/lctrts/lctes2012.html#SbirleaZBCS12

Jason Cong Glenn Reinman Alex A. T. Bui Vivek Sarkar Customizable Domain-Specific Computing. 6-15 2011 28 IEEE Des. Test Comput. 2 https://doi.org/10.1109/MDT.2010.141 http://doi.ieeecomputersociety.org/10.1109/MDT.2010.141 db/journals/dt/dt28.html#CongRBS11

Kan Wang 0003 Sheqin Dong Yuchun Ma Yu Wang 0002 Xianlong Hong Jason Cong Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. 2490-2498 2011 94-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1587/transfun.E94.A.2490 http://search.ieice.org/bin/summary.php?id=e94-a_12_2490 db/journals/ieicet/ieicet94a.html#WangDMWHC11

Jason Cong Overview of Center for Domain-Specific Computing. 632-635 2011 26 J. Comput. Sci. Technol. 4 https://doi.org/10.1007/s11390-011-1163-2 db/journals/jcst/jcst26.html#Cong11

Jason Cong Bin Liu 0006 Stephen Neuendorffer Juanjo Noguera Kees A. Vissers Zhiru Zhang High-Level Synthesis for FPGAs: From Prototyping to Deployment. 473-491 2011 30 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2011.2110592 db/journals/tcad/tcad30.html#CongLNNVZ11

Jason Cong Hui Huang 0001 Wei Jiang 0035 Pattern-Mining for Behavioral Synthesis. 939-944 2011 30 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/TCAD.2011.2106370 db/journals/tcad/tcad30.html#CongHJ11

Jason Cong Wei Jiang 0035 Bin Liu 0006 Yi Zou Automatic memory partitioning and scheduling for throughput and power optimization. 15:1-15:25 2011 16 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/1929943.1929947 db/journals/todaes/todaes16.html#CongJLZ11

Jeonghun Kim Hanjun Choi Sungyeal Yoon Taesik Bang Jongchan Park Chaehyun Jung Jason Cong An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. 1490-1495 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2010.2051568 db/journals/tvlsi/tvlsi19.html#KimCYBPJC11

Jason Cong Era of customization and specialization. 3 2011 ASAP https://doi.org/10.1109/ASAP.2011.6043228 https://doi.ieeecomputersociety.org/10.1109/ASAP.2011.6043228 conf/asap/2011 db/conf/asap/asap2011.html#Cong11 Jason Cong Beayna Grigorian Glenn Reinman Marco Vitanza Accelerating vision and navigation applications on a customizable platform. 25-32 2011 ASAP https://doi.org/10.1109/ASAP.2011.6043233 https://doi.ieeecomputersociety.org/10.1109/ASAP.2011.6043233 conf/asap/2011 db/conf/asap/asap2011.html#CongGRV11 Jason Cong Karthik Gururaj Muhuan Huang Sen Li Bingjun Xiao Yi Zou Domain-specific processor with 3D integration for medical image processing. 247-250 2011 ASAP https://doi.org/10.1109/ASAP.2011.6043279 https://doi.ieeecomputersociety.org/10.1109/ASAP.2011.6043279 conf/asap/2011 db/conf/asap/asap2011.html#CongGHLXZ11 Kan Wang 0003 Yuchun Ma Sheqin Dong Yu Wang 0002 Xianlong Hong Jason Cong Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. 261-266 2011 ASP-DAC https://doi.org/10.1109/ASPDAC.2011.5722195 http://dl.acm.org/citation.cfm?id=1950875 conf/aspdac/2011 db/conf/aspdac/aspdac2011.html#WangMDWHC11 Yu-Ting Chen 0003 Jason Cong Glenn Reinman HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. 295-304 2011 CODES+ISSS https://doi.org/10.1145/2039370.2039416 conf/codes/2011 db/conf/codes/codes2011.html#ChenCR11 Jason Cong Guojie Luo Yiyu Shi 0001 Thermal-aware cell and through-silicon-via co-placement for 3D ICs. 670-675 2011 DAC https://doi.org/10.1145/2024724.2024876 conf/dac/2011 db/conf/dac/dac2011.html#CongLS11 Jason Cong Hui Huang 0001 Chunyue Liu Yi Zou A reuse-aware prefetching scheme for scratchpad memory. 960-965 2011 DAC https://doi.org/10.1145/2024724.2024937 conf/dac/2011 db/conf/dac/dac2011.html#CongHLZ11 Alexandros Papakonstantinou Yun Liang 0001 John A. Stratton Karthik Gururaj Deming Chen Wen-mei W. Hwu Jason Cong Multilevel Granularity Parallelism Synthesis on FPGAs. 178-185 2011 FCCM https://doi.org/10.1109/FCCM.2011.29 https://doi.ieeecomputersociety.org/10.1109/FCCM.2011.29 conf/fccm/2011 db/conf/fccm/fccm2011.html#PapakonstantinouLSGCHC11 Jason Cong Yi Zou Resolving implicit barrier synchronizations in FPGA HLS (abstract only). 278 2011 FPGA https://doi.org/10.1145/1950413.1950469 https://www.wikidata.org/entity/Q130866249 conf/fpga/2011 db/conf/fpga/fpga2011.html#CongZ11 Jason Cong Muhuan Huang Yi Zou Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. 50-57 2011 FPL https://doi.org/10.1109/FPL.2011.20 https://doi.ieeecomputersociety.org/10.1109/FPL.2011.20 conf/fpl/2011 db/conf/fpl/fpl2011.html#CongHZ11 Jason Cong Karthik Gururaj Assuring application-level correctness against soft errors. 150-157 2011 ICCAD https://doi.org/10.1109/ICCAD.2011.6105319 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2011.6105319 http://dl.acm.org/citation.cfm?id=2132360 conf/iccad/2011 db/conf/iccad/iccad2011.html#CongG11 Jason Cong Peng Zhang 0007 Yi Zou Combined loop transformation and hierarchy allocation for data reuse optimization. 185-192 2011 ICCAD https://doi.org/10.1109/ICCAD.2011.6105324 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2011.6105324 http://dl.acm.org/citation.cfm?id=2132368 conf/iccad/2011 db/conf/iccad/iccad2011.html#CongZZ11 Jason Cong Yuhui Huang Bo Yuan ATree-based topology synthesis for on-chip network. 651-658 2011 ICCAD https://doi.org/10.1109/ICCAD.2011.6105399 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2011.6105399 http://dl.acm.org/citation.cfm?id=2132471 conf/iccad/2011 db/conf/iccad/iccad2011.html#CongHY11 Kanit Therdsteerasukdi Gyungsu Byun Jeremy Ir Glenn Reinman Jason Cong M. Frank Chang The DIMM tree architecture: A high bandwidth and scalable memory system. 388-395 2011 ICCD https://doi.org/10.1109/ICCD.2011.6081428 https://doi.ieeecomputersociety.org/10.1109/ICCD.2011.6081428 https://www.wikidata.org/entity/Q59616257 conf/iccd/2011 db/conf/iccd/iccd2011.html#TherdsteerasukdiBIRCC11 Jason Cong John Lee 0002 Guojie Luo A unified optimization framework for simultaneous gate sizing and placement under density constraints. 1207-1210 2011 ISCAS https://doi.org/10.1109/ISCAS.2011.5937786 conf/iscas/2011 db/conf/iscas/iscas2011.html#CongLL11 Jason Cong Karthik Gururaj Hui Huang 0001 Chunyue Liu Glenn Reinman Yi Zou An energy-efficient adaptive hybrid cache. 67-72 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016825&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#CongGHLRZ11 Gyungsu Byun Yanghyo Kim Jongsun Kim Sai-Wang Tam Hsieh-Hung Hsieh P.-Y. Wu Chewnpu Jou Jason Cong Glenn Reinman Mau-Chung Frank Chang An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. 488-490 2011 ISSCC https://doi.org/10.1109/ISSCC.2011.5746409 https://www.wikidata.org/entity/Q59616250 conf/isscc/2011 db/conf/isscc/isscc2011.html#ByunKKTHWJCRC11 Ming Yan 0006 Jianwen Chen Luminita A. Vese John D. Villasenor Alex A. T. Bui Jason Cong EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. 1-10 2011 ISVC (1) https://doi.org/10.1007/978-3-642-24028-7_1 conf/isvc/2011-1 db/conf/isvc/isvc2011-1.html#YanCVVBC11 Jason Cong Bingjun Xiao mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. 1-8 2011 NANOARCH https://doi.org/10.1109/NANOARCH.2011.5941476 https://doi.ieeecomputersociety.org/10.1109/NANOARCH.2011.5941476 http://dl.acm.org/citation.cfm?id=2052098 conf/nanoarch/2011 db/conf/nanoarch/nanoarch2011.html#CongX11 Jason Cong Muhuan Huang Yi Zou 3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. 70-73 2011 SASP https://doi.org/10.1109/SASP.2011.5941081 https://doi.ieeecomputersociety.org/10.1109/SASP.2011.5941081 conf/sasp/2011 db/conf/sasp/sasp2011.html#CongHZ11 Sai-Wang Tam Eran Socher Mau-Chung Frank Chang Jason Cong Glenn D. Reinman RF-Interconnect for Future Network-On-Chip. 255-280 2011 Low Power Networks-on-Chip https://doi.org/10.1007/978-1-4419-6911-8_10 https://www.wikidata.org/entity/Q59616254 books/sp/SLP2011 db/books/collections/SLP2011.html#TamSCCR11

Robert K. Brayton Jason Cong NSF Workshop on EDA: Past, Present, and Future (Part 1). 68-74 2010 27 IEEE Des. Test Comput. 2 https://doi.org/10.1109/MDT.2010.51 http://doi.ieeecomputersociety.org/10.1109/MDT.2010.51 https://www.wikidata.org/entity/Q126126989 db/journals/dt/dt27.html#BraytonC10

Robert K. Brayton Jason Cong NSF Workshop on EDA: Past, Present, and Future (Part 2). 62-74 2010 27 IEEE Des. Test Comput. 3 https://doi.org/10.1109/MDT.2010.70 http://doi.ieeecomputersociety.org/10.1109/MDT.2010.70 db/journals/dt/dt27.html#BraytonC10a

Jason Cong Guojie Luo Advances and Challenges in 3D Physical Design. 321-337 2010 5 Inf. Media Technol. 2 https://doi.org/10.11185/imt.5.321 db/journals/imt/imt5.html#CongL10

Jason Cong Guojie Luo Advances and Challenges in 3D Physical Design. 2-18 2010 3 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.3.2 db/journals/ipsj/ipsj3.html#CongL10

Deming Chen Jason Cong Chen Dong 0003 Lei He 0001 Fei Li 0003 Chi-Chen Peng Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. 1709-1722 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2010.2061770 db/journals/tcad/tcad29.html#ChenCDHLP10

Jason Cong Puneet Gupta 0001 John Lee 0002 Evaluating Statistical Power Optimization. 1750-1762 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2010.2061390 db/journals/tcad/tcad29.html#CongGL10

Jason Cong Bin Liu 0006 Rupak Majumdar Zhiru Zhang Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. 4:1-4:29 2010 16 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/1870109.1870113 db/journals/todaes/todaes16.html#CongLMZ10

Deming Chen Jason Cong Yiping Fan Lu Wan LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. 564-577 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2009.2013353 db/journals/tvlsi/tvlsi18.html#ChenCFW10

Thorlindur Thorolfsson Guojie Luo Jason Cong Paul D. Franzon Logic-on-logic 3D integration and placement. 1-4 2010 3DIC https://doi.org/10.1109/3DIC.2010.5751451 conf/3dic/2010 db/conf/3dic/3dic2010.html#ThorolfssonLCF10 Jason Cong Chunyue Liu Glenn Reinman ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. 443-448 2010 DAC https://doi.org/10.1145/1837274.1837385 conf/dac/2010 db/conf/dac/dac2010.html#CongLR10 Jason Cong Kirill Minkovich LUT-based FPGA technology mapping for reliability. 517-522 2010 DAC https://doi.org/10.1145/1837274.1837401 https://www.wikidata.org/entity/Q130897764 conf/dac/2010 db/conf/dac/dac2010.html#CongM10 Jason Cong Hui Huang 0001 Wei Jiang 0035 A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. 1255-1260 2010 DATE https://doi.org/10.1109/DATE.2010.5456999 http://dl.acm.org/citation.cfm?id=1871228 conf/date/2010 db/conf/date/date2010.html#CongHJ10 Jason Cong Bin Liu 0006 Junjuan Xu Coordinated resource optimization in behavioral synthesis. 1267-1272 2010 DATE https://doi.org/10.1109/DATE.2010.5457001 http://dl.acm.org/citation.cfm?id=1871230 conf/date/2010 db/conf/date/date2010.html#CongLX10 Jason Cong Yi Zou A Comparative Study on the Architecture Templates for Dynamic Nested Loops. 251-254 2010 FCCM https://doi.org/10.1109/FCCM.2010.45 https://doi.ieeecomputersociety.org/10.1109/FCCM.2010.45 conf/fccm/2010 db/conf/fccm/fccm2010.html#CongZ10 Jiyu Zhang Zhiru Zhang Sheng Zhou Mingxing Tan Xianhua Liu 0001 Xu Cheng 0001 Jason Cong Bit-level optimization for high-level synthesis and FPGA-based acceleration. 59-68 2010 FPGA https://doi.org/10.1145/1723112.1723124 https://www.wikidata.org/entity/Q130871161 conf/fpga/2010 db/conf/fpga/fpga2010.html#ZhangZZTLCC10 Jason Cong Karthik Gururaj Wei Jiang 0035 Bin Liu 0006 Kirill Minkovich Bo Yuan Yi Zou Accelerating Monte Carlo based SSTA using FPGA. 111-114 2010 FPGA https://doi.org/10.1145/1723112.1723132 https://www.wikidata.org/entity/Q130866279 conf/fpga/2010 db/conf/fpga/fpga2010.html#CongGJLMYZ10 Jason Cong Kirill Minkovich LUT-based FPGA technology mapping for reliability (abstract only). 288 2010 FPGA https://doi.org/10.1145/1723112.1723177 https://www.wikidata.org/entity/Q130879750 conf/fpga/2010 db/conf/fpga/fpga2010.html#CongM10 Jason Cong Guojie Luo An analytical placer for mixed-size 3D placement. 61-66 2010 ISPD https://doi.org/10.1145/1735023.1735044 conf/ispd/2010 db/conf/ispd/ispd2010.html#CongL10

Jason Cong Wolfgang Rosenstiel The Last Byte: The HLS tipping point. 104 2009 26 IEEE Des. Test Comput. 4 https://doi.org/10.1109/MDT.2009.88 http://doi.ieeecomputersociety.org/10.1109/MDT.2009.88 https://www.wikidata.org/entity/Q113272699 db/journals/dt/dt26.html#CongR09

Jason Cong Yiping Fan Junjuan Xu Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. 2009 14 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/1529255.1529257 db/journals/todaes/todaes14.html#CongFX09 35:1-35:31

Jason Cong Yi Zou FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. 2009 2 ACM Trans. Reconfigurable Technol. Syst. 3 https://doi.org/10.1145/1575774.1575776 https://www.wikidata.org/entity/Q130890521 db/journals/trets/trets2.html#CongZ09 17:1-17:29

Jason Cong Karthik Gururaj Guoling Han Wei Jiang 0035 Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. 1318-1329 2009 17 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2008.2004874 db/journals/tvlsi/tvlsi17.html#CongGHJ09

Jason Cong Puneet Gupta 0001 John Lee 0002 On the futility of statistical power optimization. 167-172 2009 ASP-DAC https://doi.org/10.1109/ASPDAC.2009.4796475 http://dl.acm.org/citation.cfm?id=1509686 conf/aspdac/2009 db/conf/aspdac/aspdac2009.html#CongGL09 Jason Cong Guojie Luo A multilevel analytical placement for 3D ICs. 361-366 2009 ASP-DAC https://doi.org/10.1109/ASPDAC.2009.4796507 http://dl.acm.org/citation.cfm?id=1509725 conf/aspdac/2009 db/conf/aspdac/aspdac2009.html#CongL09 Jason Cong Albert Liu Bin Liu 0006 A variation-tolerant scheduler for better than worst-case behavioral synthesis. 221-228 2009 CODES+ISSS https://doi.org/10.1145/1629435.1629467 conf/codes/2009 db/conf/codes/codes2009.html#CongLL09 Jason Cong N. S. Nagaraj Ruchir Puri William H. Joyner Jeff Burns Moshe Gavrielov Riko Radojcic Peter Rickert Hans Stork Moore's Law: another casualty of the financial meltdown? 202-203 2009 DAC https://doi.org/10.1145/1629911.1629966 conf/dac/2009 db/conf/dac/dac2009.html#CongNPJBGRRS09 Ruchir Puri Eshel Haritan Stan Krolikoski Jason Cong Tim Kogel Bradley D. McCredie John Shen Andrés Takach From milliwatts to megawatts: system level power challenge. 750-751 2009 DAC https://doi.org/10.1145/1629911.1630105 conf/dac/2009 db/conf/dac/dac2009.html#PuriHKCKMST09 Jason Cong Karthik Gururaj Energy efficient multiprocessor task scheduling under input-dependent variation. 411-416 2009 DATE https://doi.org/10.1109/DATE.2009.5090698 http://dl.acm.org/citation.cfm?id=1874719 conf/date/2009 db/conf/date/date2009.html#CongG09 Jason Cong Karthik Gururaj Bin Liu 0006 Chunyue Liu Zhiru Zhang Sheng Zhou Yi Zou Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. 231-234 2009 FCCM https://doi.org/10.1109/FCCM.2009.35 https://doi.ieeecomputersociety.org/10.1109/FCCM.2009.35 conf/fccm/2009 db/conf/fccm/fccm2009.html#CongGLLZZZ09 Jason Cong Karthik Gururaj Guoling Han Synthesis of reconfigurable high-performance multicore systems. 201-208 2009 FPGA https://doi.org/10.1145/1508128.1508159 conf/fpga/2009 db/conf/fpga/fpga2009.html#CongGH09 Jason Cong Karthik Gururaj Bin Liu 0006 Chunyue Liu Yi Zou Zhiru Zhang Sheng Zhou Revisiting bitwidth optimizations. 278 2009 FPGA https://doi.org/10.1145/1508128.1508182 conf/fpga/2009 db/conf/fpga/fpga2009.html#CongGLLZZZ09 Jason Cong Customizable domain-specific computing. 1 2009 FPL https://doi.org/10.1109/FPL.2009.5272570 conf/fpl/2009 db/conf/fpl/fpl2009.html#Cong09 Jason Cong Bin Liu 0006 Zhiru Zhang Scheduling with soft constraints. 47-54 2009 ICCAD https://doi.org/10.1145/1687399.1687410 https://ieeexplore.ieee.org/document/5361315/ conf/iccad/2009 db/conf/iccad/iccad2009.html#CongLZ09 Tony F. Chan Jason Cong Eric Radke A rigorous framework for convergent net weighting schemes in timing-driven placement. 288-294 2009 ICCAD https://doi.org/10.1145/1687399.1687454 https://ieeexplore.ieee.org/document/5361277/ conf/iccad/2009 db/conf/iccad/iccad2009.html#ChanCR09 Jason Cong Yi Zou Parallel multi-level analytical global placement on graphics processing units. 681-688 2009 ICCAD https://doi.org/10.1145/1687399.1687525 https://ieeexplore.ieee.org/document/5361221/ conf/iccad/2009 db/conf/iccad/iccad2009.html#CongZ09 Jason Cong Wei Jiang 0035 Bin Liu 0006 Yi Zou Automatic memory partitioning and scheduling for throughput and power optimization. 697-704 2009 ICCAD https://doi.org/10.1145/1687399.1687528 https://ieeexplore.ieee.org/document/5361219/ conf/iccad/2009 db/conf/iccad/iccad2009.html#CongJLZ09 Alexandros Papakonstantinou Karthik Gururaj John A. Stratton Deming Chen Jason Cong Wen-mei W. Hwu High-performance CUDA kernel execution on FPGAs. 515-516 2009 ICS https://doi.org/10.1145/1542275.1542357 https://www.wikidata.org/entity/Q131113599 conf/ics/2009 db/conf/ics/ics2009.html#PapakonstantinouGSCCH09 Jason Cong Bin Liu 0006 Zhiru Zhang Behavior-level observability don't-cares and application to low-power behavioral synthesis. 139-144 2009 ISLPED https://doi.org/10.1145/1594233.1594266 conf/islped/2009 db/conf/islped/islped2009.html#CongLZ09 Suk-Bok Lee Sai-Wang Tam Ioannis Pefkianakis Songwu Lu M. Frank Chang Chuanxiong Guo Glenn Reinman Chunyi Peng 0001 Mishali Naik Lixia Zhang 0001 Jason Cong A scalable micro wireless interconnect structure for CMPs. 217-228 2009 MobiCom https://doi.org/10.1145/1614320.1614345 https://www.wikidata.org/entity/Q59616271 conf/mobicom/2009 db/conf/mobicom/mobicom2009.html#LeeTPLCGRPNZC09 Alexandros Papakonstantinou Karthik Gururaj John A. Stratton Deming Chen Jason Cong Wen-mei W. Hwu FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. 35-42 2009 SASP https://doi.org/10.1109/SASP.2009.5226333 https://doi.ieeecomputersociety.org/10.1109/SASP.2009.5226333 conf/sasp/2009 db/conf/sasp/sasp2009.html#PapakonstantinouGSCCH09 Jason Cong Mau-Chung Frank Chang Glenn Reinman Sai-Wang Tam Multiband RF-interconnect for reconfigurable network-on-chip communications. 107-108 2009 SLIP https://doi.org/10.1145/1572471.1572491 https://www.wikidata.org/entity/Q59616558 conf/slip/2009 db/conf/slip/slip2009.html#CongCRT09

Yuan Xie 0001 Jason Cong Paul D. Franzon Editorial: Special issue on 3D integrated circuits and microarchitectures. 2008 4 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/1412587.1412588 db/journals/jetc/jetc4.html#XieCF08 15:1-15:2

Yuchun Ma Yongxiang Liu Eren Kursun Glenn Reinman Jason Cong Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. 2008 4 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/1412587.1412590 db/journals/jetc/jetc4.html#MaLKRC08 17:1-17:30

Jason Cong Min Xie 0004 A Robust Mixed-Size Legalization and Detailed Placement Algorithm. 1349-1362 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/TCAD.2008.925792 db/journals/tcad/tcad27.html#CongX08

Jason Cong Guojie Luo Eric Radke Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. 2133-2144 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2008.2006158 db/journals/tcad/tcad27.html#CongLR08

Cheng-Tao Hsieh Jason Cong Zhiru Zhang Shih-Chieh Chang 0001 Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. 10-15 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483919 http://dl.acm.org/citation.cfm?id=1356807 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#HsiehCZC08 Wei Jiang 0035 Zhiru Zhang Miodrag Potkonjak Jason Cong Scheduling with integer time budgeting for low-power optimization. 22-27 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483947 http://dl.acm.org/citation.cfm?id=1356809 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#JiangZPC08 Xin Li Yuchun Ma Xianlong Hong Sheqin Dong Jason Cong LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. 209-212 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483942 http://dl.acm.org/citation.cfm?id=1356856 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#LiMHDC08 Jason Cong Junjuan Xu Simultaneous FU and Register Binding Based on Network Flow Method. 1057-1062 2008 DATE https://doi.org/10.1109/DATE.2008.4484821 https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484821 https://doi.org/10.1145/1403375.1403629 conf/date/2008 db/conf/date/date2008.html#CongX08 Kirill Minkovich Jason Cong Mapping for better than worst-case delays in LUT-based FPGA designs. 56-64 2008 FPGA https://doi.org/10.1145/1344671.1344681 conf/fpga/2008 db/conf/fpga/fpga2008.html#MinkovichC08 Jason Cong Yi Zou Lithographic aerial image simulation with FPGA-based hardwareacceleration. 67-76 2008 FPGA https://doi.org/10.1145/1344671.1344683 https://www.wikidata.org/entity/Q130877677 conf/fpga/2008 db/conf/fpga/fpga2008.html#CongZ08 Jason Cong Wei Jiang 0035 Pattern-based behavior synthesis for FPGA resource reduction. 107-116 2008 FPGA https://doi.org/10.1145/1344671.1344688 https://www.wikidata.org/entity/Q130876031 conf/fpga/2008 db/conf/fpga/fpga2008.html#CongJ08 M. Frank Chang Jason Cong Adam Kaplan Mishali Naik Glenn Reinman Eran Socher Sai-Wang Tam CMP network-on-chip overlaid with multi-band RF-interconnect. 191-202 2008 HPCA https://doi.org/10.1109/HPCA.2008.4658639 https://www.wikidata.org/entity/Q59616296 conf/hpca/2008 db/conf/hpca/hpca2008.html#ChangCKNRST08 Jason Cong Karthik Gururaj Guoling Han Adam Kaplan Mishali Naik Glenn Reinman MC-Sim: an efficient simulation tool for MPSoC designs. 364-371 2008 ICCAD https://doi.org/10.1109/ICCAD.2008.4681599 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2008.4681599 https://dl.acm.org/citation.cfm?id=1509541 conf/iccad/2008 db/conf/iccad/iccad2008.html#CongGHKNR08 Amit Agarwal Jason Cong Brian Tagiku Fault tolerant placement and defect reconfiguration for nano-FPGAs. 714-721 2008 ICCAD https://doi.org/10.1109/ICCAD.2008.4681655 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2008.4681655 https://dl.acm.org/citation.cfm?id=1509612 conf/iccad/2008 db/conf/iccad/iccad2008.html#AgarwalCT08 Jason Cong John Lee 0002 Lieven Vandenberghe Robust gate sizing via mean excess delay minimization. 10-14 2008 ISPD https://doi.org/10.1145/1353629.1353634 conf/ispd/2008 db/conf/ispd/ispd2008.html#CongLV08 Jason Cong Guojie Luo Highly efficient gradient computation for density-constrained analytical placement methods. 39-46 2008 ISPD https://doi.org/10.1145/1353629.1353639 conf/ispd/2008 db/conf/ispd/ispd2008.html#CongL08 M.-C. Frank Chang Eran Socher Sai-Wang Tam Jason Cong Glenn Reinman RF interconnects for communications on-chip. 78-83 2008 ISPD https://doi.org/10.1145/1353629.1353649 https://www.wikidata.org/entity/Q59616571 conf/ispd/2008 db/conf/ispd/ispd2008.html#ChangSTCR08 M.-C. Frank Chang Jason Cong Adam Kaplan Chunyue Liu Mishali Naik Jagannath Premkumar Glenn Reinman Eran Socher Sai-Wang Tam Power reduction of CMP communication networks via RF-interconnects. 376-387 2008 MICRO https://doi.org/10.1109/MICRO.2008.4771806 https://doi.ieeecomputersociety.org/10.1109/MICRO.2008.4771806 http://dl.acm.org/citation.cfm?id=1521818 https://www.wikidata.org/entity/Q59616570 conf/micro/2008 db/conf/micro/micro2008.html#ChangCKLNPRST08 Jason Cong A new generation of C-base synthesis tool and domain-specific computing. 386 2008 SoCC https://doi.org/10.1109/SOCC.2008.4641556 conf/socc/2008 db/conf/socc/socc2008.html#Cong08 Jason Cong Yuzheng Ding FPGA Technology Mapping. 2008 Encyclopedia of Algorithms https://doi.org/10.1007/978-0-387-30162-4_148 reference/algo/2008 db/reference/algo/algo2008.html#CongD08 Jason Cong Joseph R. Shinnerl Enhancing Placement with Multilevel Techniques. 2008 Handbook of Algorithms for Physical Design Automation https://doi.org/10.1201/9781420013481.ch19 reference/crc/2008apda db/reference/crc/apda2008.html#CongS08

Jason Cong Kirill Minkovich Optimality Study of Logic Synthesis for LUT-Based FPGAs. 230-239 2007 26 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2006.887922 db/journals/tcad/tcad26.html#CongM07

Chen Li 0004 Min Xie 0004 Cheng-Kok Koh Jason Cong Patrick H. Madden Routability-Driven Placement and White Space Allocation. 858-871 2007 26 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2007.8361580 https://doi.org/10.1109/TCAD.2006.884575 db/journals/tcad/tcad26.html#LiXKCM07

Jason Cong Guoling Han Ashok Jagannathan Glenn Reinman Krzysztof Rutkowski Accelerating Sequential Applications on CMPs Using Core Spilling. 1094-1107 2007 18 IEEE Trans. Parallel Distributed Syst. 8 https://doi.org/10.1109/TPDS.2007.1085 http://doi.ieeecomputersociety.org/10.1109/TPDS.2007.1085 db/journals/tpds/tpds18.html#CongHJRR07

Deming Chen Jason Cong Yiping Fan Zhiru Zhang High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. 529-534 2007 conf/aspdac/2007 ASP-DAC https://doi.org/10.1109/ASPDAC.2007.358040 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358040 http://dl.acm.org/citation.cfm?id=1323437 db/conf/aspdac/aspdac2007.html#ChenCFZ07 Jason Cong Guojie Luo Jie Wei Yan Zhang Thermal-Aware 3D IC Placement Via Transformation. 780-785 2007 conf/aspdac/2007 ASP-DAC https://doi.org/10.1109/ASPDAC.2007.358084 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358084 http://dl.acm.org/citation.cfm?id=1323523 db/conf/aspdac/aspdac2007.html#CongLWZ07 Yuchun Ma Zhuoyuan Li 0003 Jason Cong Xianlong Hong Glenn Reinman Sheqin Dong Qiang Zhou 0001 Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. 920-925 2007 conf/aspdac/2007 ASP-DAC https://doi.org/10.1109/ASPDAC.2007.358107 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358107 http://dl.acm.org/citation.cfm?id=1323400 db/conf/aspdac/aspdac2007.html#MaLCHRDZ07 Jason Cong Guoling Han Wei Jiang 0035 Synthesis of an application-specific soft multiprocessor system. 99-107 2007 conf/fpga/2007 FPGA https://doi.org/10.1145/1216919.1216934 db/conf/fpga/fpga2007.html#CongHJ07 Jason Cong Kirill Minkovich Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. 139-147 2007 conf/fpga/2007 FPGA https://doi.org/10.1145/1216919.1216944 db/conf/fpga/fpga2007.html#CongM07 Yongxiang Liu Yuchun Ma Eren Kursun Glenn Reinman Jason Cong Fine grain 3D integration for microarchitecture design through cube packing exploration. 259-266 2007 ICCD https://doi.org/10.1109/ICCD.2007.4601911 https://doi.ieeecomputersociety.org/10.1109/ICCD.2007.4601911 conf/iccd/2007 db/conf/iccd/iccd2007.html#LiuMKRC07 Jason Cong Michalis Romesis Joseph R. Shinnerl Kenton Sze Min Xie 0004 Locality and Utilization in Placement Suboptimality. 13-36 2007 Modern Circuit Placement https://doi.org/10.1007/978-0-387-68739-1_2 books/sp/NC2007 db/books/collections/NC2007.html#CongRSS007 Gi-Joon Nam Jason Cong Modern Circuit Placement, Best Practices and Results Springer 2007 978-0-387-36837-5 978-0-387-68739-1 https://doi.org/10.1007/978-0-387-68739-1 db/books/collections/NC2007.html Joseph R. Shinnerl Jason Cong Large-Scale Global Placement. 2007 Handbook of Approximation Algorithms and Metaheuristics https://doi.org/10.1201/9781420010749.ch79 reference/crc/2007aam db/reference/crc/aam2007.html#ShinnerlC07

Deming Chen Jason Cong Peichen Pan FPGA Design Automation: A Survey. 2006 1 Found. Trends Electron. Des. Autom. 3 https://doi.org/10.1561/1000000003 db/journals/fteda/fteda1.html#ChenCP06

Jason Cong Michail Romesis Joseph R. Shinnerl Fast floorplanning by look-ahead enabled recursive bipartitioning. 1719-1732 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/TCAD.2005.859519 db/journals/tcad/tcad25.html#CongRS06

Darko Kirovski Yean-Yow Hwang Miodrag Potkonjak Jason Cong Protecting Combinational Logic Synthesis Solutions. 2687-2696 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2006.882490 db/journals/tcad/tcad25.html#KirovskiHPC06

Deming Chen Jason Cong Junjuan Xu Optimal simultaneous module and multivoltage assignment for low power. 362-386 2006 11 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/1142155.1142161 db/journals/todaes/todaes11.html#ChenCX06

Gang Chen 0020 Jason Cong Simultaneous placement with clustering and duplication. 740-772 2006 11 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/1142980.1142989 db/journals/todaes/todaes11.html#ChenC06

Jason Cong Guoling Han Zhiru Zhang Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. 986-997 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2006.884050 db/journals/tvlsi/tvlsi14.html#CongHZ06

Jason Cong Min Xie 0004 A robust detailed placement for mixed-size IC designs. 188-194 2006 conf/aspdac/2006 ASP-DAC https://doi.org/10.1109/ASPDAC.2006.1594680 https://doi.org/10.1145/1118299.1118353 db/conf/aspdac/aspdac2006.html#CongX06 Jason Cong Ashok Jagannathan Yuchun Ma Glenn Reinman Jie Wei Yan Zhang An automated design flow for 3D microarchitecture evaluation. 384-389 2006 conf/aspdac/2006 ASP-DAC https://doi.org/10.1109/ASPDAC.2006.1594713 https://doi.org/10.1145/1118299.1118395 db/conf/aspdac/aspdac2006.html#CongJMRWZ06 Jason Cong Zhiru Zhang An efficient and versatile scheduling algorithm based on SDC formulation. 433-438 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147025 db/conf/dac/dac2006.html#CongZ06 Joey Y. Lin Deming Chen Jason Cong Optimal simultaneous mapping and clustering for FPGA delay optimization. 472-477 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147035 db/conf/dac/dac2006.html#LinCC06 Deming Chen Jason Cong Yiping Fan Junjuan Xu Optimality study of resource binding with multi-Vdds. 580-585 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147059 db/conf/dac/dac2006.html#ChenCFX06 Jason Cong Yiping Fan Guoling Han Wei Jiang 0035 Zhiru Zhang Behavior and communication co-optimization for systems with sequential communication media. 675-678 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147080 db/conf/dac/dac2006.html#CongFHJZ06 Jason Cong Kirill Minkovich Optimality study of logic synthesis for LUT-based FPGAs. 33-40 2006 conf/fpga/2006 FPGA https://doi.org/10.1145/1117201.1117207 db/conf/fpga/fpga2006.html#CongM06 Jason Cong Yiping Fan Wei Jiang 0035 Platform-based resource binding using a distributed register-file microarchitecture. 709-715 2006 conf/iccad/2006 ICCAD https://doi.org/10.1145/1233501.1233648 https://doi.org/10.1109/ICCAD.2006.320017 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2006.320017 db/conf/iccad/iccad2006.html#CongFJ06 Tony F. Chan Jason Cong Joseph R. Shinnerl Kenton Sze Min Xie 0004 mPL6: enhanced multilevel mixed-size placement. 212-214 2006 conf/ispd/2006 ISPD https://doi.org/10.1145/1123008.1123055 db/conf/ispd/ispd2006.html#ChanCSSX06 Jason Cong Yiping Fan Guoling Han Wei Jiang 0035 Zhiru Zhang Platform-Based Behavior-Level and System-Level Synthesis. 199-202 2006 SoCC https://doi.org/10.1109/SOCC.2006.283880 conf/socc/2006 db/conf/socc/socc2006.html#CongFHJZ06

Jason Cong Jie Fang Min Xie 0004 Yan Zhang MARS-a multilevel full-chip gridless routing system. 382-394 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2004.842803 db/journals/tcad/tcad24.html#CongFXZ05

Fei Li 0003 Yizhou Lin Lei He 0001 Deming Chen Jason Cong Power modeling and characteristics of field programmable gate arrays. 1712-1724 2005 24 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/TCAD.2005.852293 db/journals/tcad/tcad24.html#LiLHCC05

Jason Cong Hui Huang 0001 Xin Yuan 0005 Technology mapping and architecture evalution for <i>k/m</i>-macrocell-based FPGAs. 3-23 2005 10 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/1044111.1044113 db/journals/todaes/todaes10.html#CongHY05

Jason Cong Joseph R. Shinnerl Min Xie 0004 Tim Kong Xin Yuan 0005 Large-scale circuit placement. 389-430 2005 10 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/1059876.1059886 db/journals/todaes/todaes10.html#CongSXKY05

Ashok Jagannathan Hannah Honghua Yang Kris Konigsfeld Dan Milliron Mosur Mohan Michail Romesis Glenn Reinman Jason Cong Microarchitecture evaluation with floorplanning and interconnect pipelining. 8-15 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1120879 https://doi.org/10.1109/ASPDAC.2005.1466114 https://www.wikidata.org/entity/Q130984372 db/conf/aspdac/aspdac2005.html#JagannathanYKMMRRC05 Jason Cong Yan Zhang Thermal-driven multilevel routing for 3-D ICs. 121-126 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1120787 https://doi.org/10.1109/ASPDAC.2005.1466143 db/conf/aspdac/aspdac2005.html#CongZ05 Deming Chen Jason Cong Junjuan Xu Optimal module and voltage assignment for low-power. 850-855 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1121054 https://doi.org/10.1109/ASPDAC.2005.1466475 db/conf/aspdac/aspdac2005.html#ChenCX05 Jason Cong Yiping Fan Guoling Han Yizhou Lin Junjuan Xu Zhiru Zhang Xu Cheng 0001 Bitwidth-aware scheduling and binding in high-level synthesis. 856-861 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1121055 https://doi.org/10.1109/ASPDAC.2005.1466476 db/conf/aspdac/aspdac2005.html#CongFHLXZC05 Jason Cong Tony Ma Ivo Bolsens Phil Moorby Jan M. Rabaey John Sanguinetti Kazutoshi Wakabayashi Yoshi Watanabe Are we ready for system-level synthesis? 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1120969 db/conf/aspdac/aspdac2005.html#CongMBMRSWW05 Jason Cong Michail Romesis Joseph R. Shinnerl Fast floorplanning by look-ahead enabled recursive bipartitioning. 1119-1122 2005 conf/aspdac/2005 ASP-DAC https://doi.org/10.1145/1120725.1120838 https://doi.org/10.1109/ASPDAC.2005.1466537 db/conf/aspdac/aspdac2005.html#CongRS05 Gang Chen 0020 Jason Cong Simultaneous timing-driven placement and duplication. 51-59 2005 conf/fpga/2005 FPGA https://doi.org/10.1145/1046192.1046200 db/conf/fpga/fpga2005.html#ChenC05 Jason Cong Yiping Fan Guoling Han Ashok Jagannathan Glenn Reinman Zhiru Zhang Instruction set extension with shadow registers for configurable processors. 99-106 2005 conf/fpga/2005 FPGA https://doi.org/10.1145/1046192.1046206 db/conf/fpga/fpga2005.html#CongFHJRZ05 Jason Cong Michail Romesis Joseph R. Shinnerl Robust mixed-size placement under tight white-space constraints. 165-172 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#CongRS05 https://doi.org/10.1109/ICCAD.2005.1560058 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560058 http://dl.acm.org/citation.cfm?id=1129624 Jason Cong Guoling Han Zhiru Zhang Architecture and compilation for data bandwidth improvement in configurable embedded processors. 263-270 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#CongHZ05 https://doi.org/10.1109/ICCAD.2005.1560075 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560075 http://dl.acm.org/citation.cfm?id=1129639 Jason Cong Yan Zhang Thermal via planning for 3-D ICs. 745-752 2005 conf/iccad/2005 ICCAD db/conf/iccad/iccad2005.html#CongZ05 https://doi.org/10.1109/ICCAD.2005.1560164 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2005.1560164 http://dl.acm.org/citation.cfm?id=1129707 Junjuan Xu Jason Cong Xu Cheng 0001 Lower-bound estimation for multi-bitwidth scheduling. 696-699 2005 conf/iscas/2005 ISCAS (1) https://doi.org/10.1109/ISCAS.2005.1464683 db/conf/iscas/iscas2005-1.html#XuCC05 Jason Cong Ashok Jagannathan Glenn Reinman Yuval Tamir Understanding the energy efficiency of SMT and CMP with multiclustering. 48-53 2005 conf/islped/2005 ISLPED https://doi.org/10.1145/1077603.1077616 db/conf/islped/islped2005.html#CongJRT05 Tony F. Chan Jason Cong Kenton Sze Multilevel generalized force-directed method for circuit placement. 185-192 2005 conf/ispd/2005 ISPD https://doi.org/10.1145/1055137.1055177 db/conf/ispd/ispd2005.html#ChanCS05 Tony F. Chan Jason Cong Michail Romesis Joseph R. Shinnerl Kenton Sze Min Xie 0004 mPL6: a robust multilevel mixed-size placement engine. 227-229 2005 conf/ispd/2005 ISPD https://doi.org/10.1145/1055137.1055185 db/conf/ispd/ispd2005.html#ChanCRSSX05

Jason Cong Sung Kyu Lim Edge separability-based circuit clustering with application to multilevel circuit partitioning. 346-357 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2004.823353 db/journals/tcad/tcad23.html#CongL04

Chin-Chih Chang Jason Cong Michail Romesis Min Xie 0004 Optimality and scalability study of existing placement algorithms. 537-549 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2004.825870 db/journals/tcad/tcad23.html#ChangCRX04

Jason Cong Yiping Fan Guoling Han Xun Yang Zhiru Zhang Architecture and synthesis for on-chip multicycle communication. 550-564 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2004.825872 db/journals/tcad/tcad23.html#CongFHYZ04

Jason Cong Sung Kyu Lim Retiming-based timing analysis with an application to mincut-based global placement. 1684-1692 2004 23 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/TCAD.2004.837718 db/journals/tcad/tcad23.html#CongL04a

Deming Chen Jason Cong Register binding and port assignment for multiplexer optimization. 68-73 2004 conf/aspdac/2004 ASP-DAC https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.173 https://dl.acm.org/citation.cfm?id=1015109 db/conf/aspdac/aspdac2004.html#ChenC04 Nitin Deo Behrooz Zahiri Ivo Bolsens Jason Cong Bhusan Gupta Philip Lopresti Christopher B. Reynolds Chris Rowen Ray Simar What happened to ASIC?: Go (recon)figure? 185 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996620 db/conf/dac/dac2004.html#DeoZBCGLRRS04 Jason Cong Yiping Fan Zhiru Zhang Architecture-level synthesis for automatic interconnect pipelining. 602-607 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996731 db/conf/dac/dac2004.html#CongFZ04 Fei Li 0003 Yan Lin 0001 Lei He 0001 Jason Cong Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. 42-50 2004 conf/fpga/2004 FPGA https://doi.org/10.1145/968280.968288 https://www.wikidata.org/entity/Q130895679 db/conf/fpga/fpga2004.html#LiLHC04 Deming Chen Jason Cong Fei Li 0003 Lei He 0001 Low-power technology mapping for FPGA architectures with dual supply voltages. 109-117 2004 conf/fpga/2004 FPGA https://doi.org/10.1145/968280.968297 db/conf/fpga/fpga2004.html#ChenCLH04 Jason Cong Yiping Fan Guoling Han Zhiru Zhang Application-specific instruction generation for configurable processor architectures. 183-189 2004 conf/fpga/2004 FPGA https://doi.org/10.1145/968280.968307 db/conf/fpga/fpga2004.html#CongFHZ04 Gang Chen 0020 Jason Cong Simultaneous Timing Driven Clustering and Placement for FPGAs. 158-167 https://doi.org/10.1007/978-3-540-30117-2_18 2004 conf/fpl/2004 FPL db/conf/fpl/fpl2004.html#ChenC04 Jason Cong Jie Wei Yan Zhang A thermal-driven floorplanning algorithm for 3D ICs. 306-313 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382591 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382591 https://dl.acm.org/citation.cfm?id=1112292 db/conf/iccad/iccad2004.html#CongWZ04 Chen Li 0004 Min Xie 0004 Cheng-Kok Koh Jason Cong Patrick H. Madden Routability-driven placement and white space allocation. 394-401 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382607 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382607 https://dl.acm.org/citation.cfm?id=1112304 db/conf/iccad/iccad2004.html#LiXKCM04 Deming Chen Jason Cong DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. 752-759 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382677 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382677 https://dl.acm.org/citation.cfm?id=1112357 db/conf/iccad/iccad2004.html#ChenC04 Deming Chen Jason Cong Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. 70-73 2004 conf/islped/2004 ISLPED https://doi.org/10.1145/1013235.1013259 db/conf/islped/islped2004.html#ChenC04 Jason Cong Gabriele Nataneli Michail Romesis Joseph R. Shinnerl An area-optimality study of floorplanning. 78-83 2004 conf/ispd/2004 ISPD https://doi.org/10.1145/981066.981083 db/conf/ispd/ispd2004.html#CongNRS04

Chin-Chih Chang Jason Cong David Zhigang Pan Xin Yuan 0005 Multilevel global placement with congestion control. 395-409 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/TCAD.2003.809661 db/journals/tcad/tcad22.html#ChangCPY03

Deming Chen Jason Cong Milos D. Ercegovac Zhijun Huang Performance-driven mapping for CPLD architectures. 1424-1431 2003 22 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2003.818120 db/journals/tcad/tcad22.html#ChenCEH03

Chin-Chih Chang Jason Cong Xin Yuan 0005 Multi-level placement for large-scale mixed-size IC designs. 325-330 2003 ASP-DAC https://doi.org/10.1145/1119772.1119835 conf/aspdac/2003 db/conf/aspdac/aspdac2003.html#ChangCY03 Chin-Chih Chang Jason Cong Min Xie 0004 Optimality and scalability study of existing placement algorithms. 621-627 2003 ASP-DAC https://doi.org/10.1145/1119772.1119914 conf/aspdac/2003 db/conf/aspdac/aspdac2003.html#ChangCX03 Jason Cong Yiping Fan Guoling Han Xun Yang Zhiru Zhang Architecture and synthesis for multi-cycle on-chip communication. 77-78 2003 conf/codes/2003 CODES+ISSS https://doi.org/10.1145/944645.944667 db/conf/codes/codes2003.html#CongFHYZ03 Jason Cong Ashok Jagannathan Glenn Reinman Michail Romesis Microarchitecture evaluation with physical planning. 32-35 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.775843 db/conf/dac/dac2003.html#CongJRR03 Jason Cong Xin Yuan 0005 Multilevel global placement with retiming. 208-213 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.775887 db/conf/dac/dac2003.html#CongY03 Fei Li 0003 Deming Chen Lei He 0001 Jason Cong Architecture evaluation for power-efficient FPGAs. 175-184 2003 conf/fpga/2003 FPGA https://doi.org/10.1145/611817.611844 db/conf/fpga/fpga2003.html#LiCHC03 Tony F. Chan Jason Cong Tim Kong Joseph R. Shinnerl Kenton Sze An Enhanced Multilevel Algorithm for Circuit Placement. 299-306 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257683 https://dl.acm.org/citation.cfm?id=1009906 db/conf/iccad/iccad2003.html#ChanCKSS03 Jason Cong Michail Romesis Min Xie 0004 Optimality and Stability Study of Timing-Driven Placement Algorithms. 472-479 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257853 https://dl.acm.org/citation.cfm?id=1009932 db/conf/iccad/iccad2003.html#CongRX03 Zhiru Zhang Yiping Fan Miodrag Potkonjak Jason Cong Gradual Relaxation Techniques with Applications to Behavioral Synthesis. 529-535 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257862 https://dl.acm.org/citation.cfm?id=1009941 db/conf/iccad/iccad2003.html#ZhangFPC03 Jason Cong Yiping Fan Guoling Han Xun Yang Zhiru Zhang Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. 536-543 2003 conf/iccad/2003 ICCAD https://doi.org/10.1109/ICCAD.2003.1257863 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257863 https://dl.acm.org/citation.cfm?id=1009942 db/conf/iccad/iccad2003.html#CongFHYZ03 Jason Cong Tim Kong Joseph R. Shinnerl Min Xie 0004 Xin Yuan 0005 Large-Scale Circuit Placement: Gap and Promise. 883-890 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257912 https://dl.acm.org/citation.cfm?id=1009991 db/conf/iccad/iccad2003.html#CongKSXY03 Deming Chen Jason Cong Yiping Fan Low-power high-level synthesis for FPGA architectures. 134-139 2003 conf/islped/2003 ISLPED https://doi.org/10.1145/871506.871541 db/conf/islped/islped2003.html#ChenCF03 Jason Cong Michail Romesis Min Xie 0004 Optimality, scalability and stability study of partitioning and placement algorithms. 88-94 2003 conf/ispd/2003 ISPD https://doi.org/10.1145/640000.640021 db/conf/ispd/ispd2003.html#CongRX03 Jason Cong Yiping Fan Xun Yang Zhiru Zhang Architecture and synthesis for multi-cycle communication. 190-196 2003 conf/ispd/2003 ISPD https://doi.org/10.1145/640000.640040 db/conf/ispd/ispd2003.html#CongFYZ03

Jason Cong David Zhigang Pan Wire width planning for interconnect performance optimization. 319-329 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.986425 db/journals/tcad/tcad21.html#CongP02

Taku Uchino Jason Cong An interconnect energy model considering coupling effects. 763-776 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2002.1013890 db/journals/tcad/tcad21.html#UchinoC02

Jason Cong Yizhou Lin Wangning Long SPFD-based global rewiring. 77-84 2002 conf/fpga/2002 FPGA https://doi.org/10.1145/503048.503060 db/conf/fpga/fpga2002.html#CongLL02 Jason Cong Min Xie 0004 Yan Zhang An enhanced multilevel routing system. 51-58 2002 conf/iccad/2002 ICCAD https://doi.org/10.1145/774572.774580 https://doi.org/10.1109/ICCAD.2002.1167513 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167513 db/conf/iccad/iccad2002.html#CongXZ02 Jason Cong Joey Y. Lin Wangning Long A new enhanced SPFD rewiring algorithm. 672-678 2002 conf/iccad/2002 ICCAD https://doi.org/10.1145/774572.774671 https://doi.org/10.1109/ICCAD.2002.1167604 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167604 db/conf/iccad/iccad2002.html#CongLL02 Chin-Chih Chang Jason Cong David Zhigang Pan Physical hierarchy generation with routing congestion control. 36-41 2002 conf/ispd/2002 ISPD https://doi.org/10.1145/505388.505399 db/conf/ispd/ispd2002.html#ChangCP02 Jason Cong Chang Wu Global clustering-based performance-driven circuit partitioning. 149-154 2002 conf/ispd/2002 ISPD https://doi.org/10.1145/505388.505424 db/conf/ispd/ispd2002.html#CongW02 Jason Cong Timing closure based on physical hierarchy. 170-174 2002 conf/ispd/2002 ISPD https://doi.org/10.1145/505388.505429 db/conf/ispd/ispd2002.html#Cong02 Jason Cong Joey Y. Lin Wangning Long Enhanced SPFD Rewiring on Improving Rewiring Ability. 91-96 2002 conf/iwls/2002 IWLS db/conf/iwls/iwls2002.html#CongLL02

Jason Cong An interconnect-centric design flow for nanometer technologies. 505-528 2001 89 Proc. IEEE 4 https://doi.org/10.1109/5.920581 db/journals/pieee/pieee89.html#Cong01

Chin-Chih Chang Jason Cong Pseudopin assignment with crosstalk noise control. 598-611 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.920686 db/journals/tcad/tcad20.html#ChangC01

Jason Cong Jie Fang Kei-Yong Khoo DUNE-a multilayer gridless routing system. 633-647 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.920694 db/journals/tcad/tcad20.html#CongFK01

Jason Cong David Zhigang Pan Interconnect performance estimation models for design planning. 739-752 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.924827 db/journals/tcad/tcad20.html#CongP01

Jason Cong Yean-Yow Hwang Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. 1077-1090 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.945303 db/journals/tcad/tcad20.html#CongH01

Jason Cong Lei He 0001 Cheng-Kok Koh David Zhigang Pan Interconnect sizing and spacing with consideration of couplingcapacitance. 1164-1169 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.945311 db/journals/tcad/tcad20.html#CongHKP01

Jason Cong Cheng-Kok Koh Patrick H. Madden Interconnect layout optimization under higher order RLC model forMCM designs. 1455-1463 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 https://doi.org/10.1109/43.969438 db/journals/tcad/tcad20.html#CongKM01

Jason Cong Tianming Kong Z. D. Pan Buffer block planning for interconnect planning and prediction. 929-937 2001 9 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/92.974906 db/journals/tvlsi/tvlsi9.html#CongKP01

Jason Cong David Zhigang Pan Prasanna V. Srinivas Improved crosstalk modeling for noise constrained interconnect optimization. 373-378 2001 conf/aspdac/2001 ASP-DAC https://doi.org/10.1145/370155.370414 db/conf/aspdac/aspdac2001.html#CongPS01 Jason Cong Michail Romesis Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. 389-394 2001 conf/dac/2001 DAC https://doi.org/10.1145/378239.378532 db/conf/dac/dac2001.html#CongR01 Taku Uchino Jason Cong An Interconnect Energy Model Considering Coupling Effects. 555-558 2001 conf/dac/2001 DAC https://doi.org/10.1145/378239.379022 db/conf/dac/dac2001.html#UchinoC01 Deming Chen Jason Cong Milos D. Ercegovac Zhijun Huang Performance-driven mapping for CPLD architectures. 39-47 2001 conf/fpga/2001 FPGA https://doi.org/10.1145/360276.360296 db/conf/fpga/fpga2001.html#ChenCEH01 Gang Chen 0020 Jason Cong Simultaneous logic decomposition with technology mapping in FPGA designs. 48-55 2001 conf/fpga/2001 FPGA https://doi.org/10.1145/360276.360298 db/conf/fpga/fpga2001.html#ChenC01 Jason Cong Jie Fang Yan Zhang VI Multilevel Approach to Full-Chip Gridless Routing. 396-403 2001 conf/iccad/2001 ICCAD https://doi.org/10.1109/ICCAD.2001.968655 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2001.968655 http://dl.acm.org/citation.cfm?id=603178 db/conf/iccad/iccad2001.html#CongFZ01

Jason Cong Jie Fang Kei-Yong Khoo Via design rule consideration in multilayer maze routing algorithms. 215-223 2000 19 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/43.828550 db/journals/tcad/tcad19.html#CongFK00

Jason Cong Songjie Xu Performance-driven technology mapping for heterogeneous FPGAs. 1268-1281 2000 19 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/43.892851 db/journals/tcad/tcad19.html#CongX00

Jason Cong Yean-Yow Hwang Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. 193-225 2000 5 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/335043.335045 db/journals/todaes/todaes5.html#CongH00

Jason Cong Songjie Xu Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. 157-162 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368596 https://doi.org/10.1109/ASPDAC.2000.835088 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835088 db/conf/aspdac/aspdac2000.html#CongX00 Jason Cong Tianming Kong Faming Liang Jun S. Liu Wing Hung Wong Dongmin Xu Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. 277-282 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368634 https://doi.org/10.1109/ASPDAC.2000.835110 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835110 db/conf/aspdac/aspdac2000.html#CongKLLWX00 Jason Cong Sung Kyu Lim Edge separability based circuit clustering with application to circuit partitioning. 429-434 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368728 https://doi.org/10.1109/ASPDAC.2000.835138 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835138 db/conf/aspdac/aspdac2000.html#CongL00 Jason Cong Sung Kyu Lim Performance driven multiway partitioning. 441-446 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368736 https://doi.org/10.1109/ASPDAC.2000.835140 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835140 db/conf/aspdac/aspdac2000.html#CongL00a Maogang Wang Sung Kyu Lim Jason Cong Majid Sarrafzadeh Multi-way partitioning using bi-partition heuristics. 667-672 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368865 https://doi.org/10.1109/ASPDAC.2000.835183 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835183 db/conf/aspdac/aspdac2000.html#WangLCS00 Jason Cong Sung Kyu Lim Chang Wu Performance driven multi-level and multiway partitioning with retiming. 274-279 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337418 db/conf/dac/dac2000.html#CongLW00 Jason Cong Hui Huang 0001 Depth optimal incremental mapping for field programmable gate arrays. 290-293 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337422 db/conf/dac/dac2000.html#CongH00 Jason Cong Xin Yuan 0005 Routing tree construction under fixed buffer locations. 379-384 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337502 db/conf/dac/dac2000.html#CongY00 Jason Cong Hui Huang 0001 Xin Yuan 0005 Technology mapping for k/m-macrocell based FPGAs. 51-59 2000 conf/fpga/2000 FPGA https://doi.org/10.1145/329166.329179 db/conf/fpga/fpga2000.html#CongHY00 Jason Cong Kenneth Yan Synthesis for FPGAs with embedded memory blocks. 75-82 2000 conf/fpga/2000 FPGA https://doi.org/10.1145/329166.329183 db/conf/fpga/fpga2000.html#CongY00 Jason Cong Sung Kyu Lim Physical Planning with Retiming. 2-7 2000 conf/iccad/2000 ICCAD db/conf/iccad/iccad2000.html#CongL00 https://doi.org/10.1109/ICCAD.2000.896441 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2000.896441 http://dl.acm.org/citation.cfm?id=602904 Tony F. Chan Jason Cong Tianming Kong Joseph R. Shinnerl Multilevel Optimization for Large-Scale Circuit Placement. 171-176 2000 conf/iccad/2000 ICCAD db/conf/iccad/iccad2000.html#ChanCKS00 https://doi.org/10.1109/ICCAD.2000.896469 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2000.896469 http://dl.acm.org/citation.cfm?id=602941 https://www.wikidata.org/entity/Q57397371 Olivier Coudert Jason Cong Sharad Malik Majid Sarrafzadeh Incremental CAD. 236-243 2000 conf/iccad/2000 ICCAD db/conf/iccad/iccad2000.html#CoudertCMS00 https://doi.org/10.1109/ICCAD.2000.896480 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2000.896480 http://dl.acm.org/citation.cfm?id=602956 Jason Cong Jie Fang Kei-Yong Khoo DUNE: a multi-layer gridless routing system with wire planning. 12-18 2000 conf/ispd/2000 ISPD https://doi.org/10.1145/332357.332367 db/conf/ispd/ispd2000.html#CongFK00 Chin-Chih Chang Jason Cong Pseudo pin assignment with crosstalk noise control. 41-47 2000 conf/ispd/2000 ISPD https://doi.org/10.1145/332357.332372 db/conf/ispd/ispd2000.html#ChangC00 Jason Cong Majid Sarrafzadeh Incremental physical design. 84-92 2000 conf/ispd/2000 ISPD https://doi.org/10.1145/332357.332379 db/conf/ispd/ispd2000.html#CongS00

Jason Cong Lei He 0001 Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. 406-420 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.752925 db/journals/tcad/tcad18.html#CongH99

Chin-Chih Chang Jason Cong An efficient approach to multilayer layer assignment with anapplication to via minimization. 608-620 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.759077 db/journals/tcad/tcad18.html#ChangC99

Jason Cong Chang Wu Optimal FPGA mapping and retiming with efficient initial state computation. 1595-1607 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/43.806805 db/journals/tcad/tcad18.html#CongW99

Jason Cong Tianming Kong Dongmin Xu Faming Liang Jun S. Liu Wing Hung Wong Relaxed Simulated Tempering for VLSI Floorplan Designs. 13-16 1999 conf/aspdac/1999 ASP-DAC https://doi.org/10.1109/ASPDAC.1999.759698 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759698 db/conf/aspdac/aspdac1999.html#CongKXLLW99 Jason Cong David Zhigang Pan Interconnect Delay Estimation Models for Synthesis and Design Planning. 97-100 1999 conf/aspdac/1999 ASP-DAC https://doi.org/10.1109/ASPDAC.1999.759720 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759720 db/conf/aspdac/aspdac1999.html#CongP99 Jason Cong Yean-Yow Hwang Songjie Xu Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. 373-378 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309963 db/conf/dac/dac99.html#CongHX99 Jason Cong Honching Li Chang Wu Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. 460-465 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309980 db/conf/dac/dac99.html#CongLW99 Jason Cong David Zhigang Pan Interconnect Estimation and Dlanning for Deep Submicron Designs. 507-510 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309988 db/conf/dac/dac99.html#CongP99 Jason Cong Chang Wu Yuzheng Ding Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. 29-35 1999 conf/fpga/1999 FPGA https://doi.org/10.1145/296399.296425 db/conf/fpga/fpga99.html#CongWD99 Jason Cong Jie Fang Kei-Yong Khoo An implicit connection graph maze routing algorithm for ECO routing. 163-167 1999 conf/iccad/1999 ICCAD https://doi.org/10.1109/ICCAD.1999.810642 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1999.810642 http://dl.acm.org/citation.cfm?id=339492.339614 db/conf/iccad/iccad1999.html#CongFK99 Jason Cong Tianming Kong David Zhigang Pan Buffer block planning for interconnect-driven floorplanning. 358-363 1999 conf/iccad/1999 ICCAD https://doi.org/10.1109/ICCAD.1999.810675 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1999.810675 http://dl.acm.org/citation.cfm?id=339492.340040 db/conf/iccad/iccad1999.html#CongKP99 Jason Cong Jie Fang Kei-Yong Khoo VIA design rule consideration in multi-layer maze routing algorithms. 214-220 1999 conf/ispd/1999 ISPD https://doi.org/10.1145/299996.300084 db/conf/ispd/ispd1999.html#CongFK99 Farid N. Najm Jason Cong David T. Blaauw Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ISLPED ACM 1999 db/conf/islped/islped1999.html 1-58113-133-X

Jason Cong Andrew B. Kahng Kwok-Shing Leung Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. 24-39 1998 17 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.673630 db/journals/tcad/tcad17.html#CongKL98

Jason Cong Chang Wu An efficient algorithm for performance-optimal FPGA technology mapping with retiming. 738-748 1998 17 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.720312 db/journals/tcad/tcad17.html#CongW98

Jason Cong Andrew B. Kahng Cheng-Kok Koh Chung-Wen Albert Tsao Bounded-skew clock and Steiner routing. 341-388 1998 3 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/293625.293628 db/journals/todaes/todaes3.html#CongKKT98

Jason Cong Chang Wu Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. 330-335 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277139 db/conf/dac/dac98.html#CongW98 Jason Cong Patrick H. Madden Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. 356-361 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277144 db/conf/dac/dac98.html#CongM98 Jason Cong Songjie Xu Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. 704-707 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277221 db/conf/dac/dac98.html#CongX98 Jason Cong Yean-Yow Hwang Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. 27-34 1998 conf/fpga/1998 FPGA https://doi.org/10.1145/275107.275116 db/conf/fpga/fpga98.html#CongH98 Jason Cong Songjie Xu Technology Mapping for FPGAs with Embedded Memory Blocks. 179-188 1998 conf/fpga/1998 FPGA https://doi.org/10.1145/275107.275138 db/conf/fpga/fpga98.html#CongX98 Robert C. Aitken Jason Cong Randy Harr Kenneth L. Shepard Wayne H. Wolf How will CAD handle billion-transistor systems? (panel). 5 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.288552 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742799 db/conf/iccad/iccad1998.html#AitkenCHSW98 Jason Cong Songjie Xu Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. 40-44 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.288558 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742848 db/conf/iccad/iccad1998.html#CongX98 Darko Kirovski Yean-Yow Hwang Miodrag Potkonjak Jason Cong Intellectual property protection by watermarking combinational logic synthesis solutions. 194-198 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.288609 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742872 db/conf/iccad/iccad1998.html#KirovskiHPC98 Jason Cong Sung Kyu Lim Multiway partitioning with pairwise movement. 512-516 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.289079 https://doi.org/10.1109/ICCAD.1998.742999 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742999 db/conf/iccad/iccad1998.html#CongL98 Jason Cong Lei He 0001 An efficient technique for device and interconnect optimization in deep submicron designs. 45-51 1998 conf/ispd/1998 ISPD https://doi.org/10.1145/274535.274542 db/conf/ispd/ispd1998.html#CongH98 Jason Cong Sinan Kaptanoglu Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998 FPGA ACM 1998 0-89791-978-5 https://doi.org/10.1145/275107 db/conf/fpga/fpga98.html

Jason Cong Patrick H. Madden Performance-driven routing with multiple sources. 410-419 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.602477 db/journals/tcad/tcad16.html#CongM97

Chin-Chih Chang Jason Cong An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. 600-603 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266294 db/conf/dac/dac97.html#ChangC97 Jason Cong Lei He 0001 Andrew B. Kahng David Noice Nagesh Shirali Steve H.-C. Yen Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. 627-632 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266303 db/conf/dac/dac97.html#CongHKNSY97 Jason Cong Chang Wu FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. 644-649 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266309 db/conf/dac/dac97.html#CongW97 Jason Cong John Peck On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. 246-248 1997 conf/fccm/1997 FCCM https://doi.org/10.1109/FPGA.1997.624629 https://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624629 db/conf/fccm/fccm1997.html#CongP97 Jason Cong Yean-Yow Hwang Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. 35-42 1997 conf/fpga/1997 FPGA https://doi.org/10.1145/258305.258310 db/conf/fpga/fpga97.html#CongH97 Jason Cong Honching Peter Li Sung Kyu Lim Toshiyuki Shibuya Dongmin Xu Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. 441-446 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643573 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643573 https://dl.acm.org/citation.cfm?id=266524 db/conf/iccad/iccad1997.html#CongLLSX97 Jason Cong David Zhigang Pan Lei He 0001 Cheng-Kok Koh Kei-Yong Khoo Interconnect design for deep submicron ICs. 478-485 1997 conf/iccad/1997 ICCAD https://dl.acm.org/citation.cfm?id=266534 db/conf/iccad/iccad1997.html#CongPHKK97 Jason Cong Lei He 0001 Cheng-Kok Koh David Zhigang Pan Global interconnect sizing and spacing with consideration of coupling capacitance. 628-633 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643604 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643604 https://dl.acm.org/citation.cfm?id=266566 db/conf/iccad/iccad1997.html#CongHKP97 Jason Cong Cheng-Kok Koh Interconnect layout optimization under higher-order RLC model. 713-720 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643617 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643617 https://dl.acm.org/citation.cfm?id=266618 db/conf/iccad/iccad1997.html#CongK97 Jason Cong Patrick H. Madden Performance driven global routing for standard cell design. 73-80 1997 conf/ispd/1997 ISPD https://doi.org/10.1145/267665.267689 db/conf/ispd/ispd1997.html#CongM97 Jason Cong Andrew B. Kahng Kwok-Shing Leung Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. 88-95 1997 conf/ispd/1997 ISPD https://doi.org/10.1145/267665.267695 db/conf/ispd/ispd1997.html#CongKL97

Jason Cong Lei He 0001 Cheng-Kok Koh Patrick H. Madden Performance optimization of VLSI interconnect layout. 1-94 1996 21 Integr. 1-2 https://doi.org/10.1016/S0167-9260(96)00008-9 db/journals/integration/integration21.html#CongHKM96

Jason Cong Wilburt Labio Narayanan Shivakumar Multiway VLSI circuit partitioning based on dual net representation. 396-409 1996 15 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.494703 db/journals/tcad/tcad15.html#CongLS96

Jason Cong Yuzheng Ding Combinational logic synthesis for LUT based field programmable gate arrays. 145-204 1996 1 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/233539.233540 db/journals/todaes/todaes1.html#CongD96

Jason Cong Lei He 0001 Optimal wiresizing for interconnects with multiple sources. 478-511 1996 1 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/238997.239018 db/journals/todaes/todaes1.html#CongH96

Jason Cong Yean-Yow Hwang Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. 726-729 1996 conf/dac/1996 DAC https://doi.org/10.1145/240518.240656 db/conf/dac/dac96.html#CongH96 Jason Cong John Peck Yuzheng Ding RASP: A General Logic Synthesis System for SRAM-Based FPGAs. 137-143 1996 conf/fpga/1996 FPGA https://doi.org/10.1145/228370.228390 db/conf/fpga/fpga96.html#CongPD96 Takumi Okamoto Jason Cong Buffered Steiner tree construction with wire sizing for interconnect layout optimization. 44-49 1996 conf/iccad/1996 ICCAD https://doi.org/10.1109/ICCAD.1996.568938 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1996.568938 https://dl.acm.org/citation.cfm?id=244530 db/conf/iccad/iccad1996.html#OkamotoC96 Jason Cong Lei He 0001 An efficient approach to simultaneous transistor and interconnect sizing. 181-186 1996 conf/iccad/1996 ICCAD https://doi.org/10.1109/ICCAD.1996.569580 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1996.569580 https://dl.acm.org/citation.cfm?id=244552 db/conf/iccad/iccad1996.html#CongH96 Jason Cong Chang Wu An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. 572-578 1996 conf/iccd/1996 ICCD https://doi.org/10.1109/ICCD.1996.563608 https://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563608 db/conf/iccd/iccd1996.html#CongW96 Jason Cong Cheng-Kok Koh Kwok-Shing Leung Simultaneous buffer and wire sizing for performance and power optimization. 271-276 1996 conf/islped/1996 ISLPED https://doi.org/10.1109/LPE.1996.547521 https://dl.acm.org/citation.cfm?id=252617 db/conf/islped/islped1996.html#CongKL96

Leonard Kleinrock Mario Gerla Nicholas Bambos Jason Cong Eli Gafni Larry Bergman Joseph A. Bannister The Supercomputer Supernet: A Scalable Distributed Terabit Network. 407-424 1995 4 J. High Speed Networks 4 https://doi.org/10.3233/JHS-1995-4406 db/journals/jhsn/jhsn4.html#KleinrockGBCGBB95

Jason Cong Kwok-Shing Leung Optimal wiresizing under Elmore delay model. 321-336 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.365123 db/journals/tcad/tcad14.html#CongL95

Kei-Yong Khoo Jason Cong An efficient multilayer MCM router based on four-via routing. 1277-1290 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/43.466343 db/journals/tcad/tcad14.html#KhooC95

Jason Cong Dongmin Xu Exploitation signal flow and logic dependency in standard cell placement. 1995 conf/aspdac/1995 ASP-DAC https://doi.org/10.1145/224818.224931 db/conf/aspdac/aspdac1995.html#CongX95 Jason Cong Yean-Yow Hwang Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. 68-74 1995 conf/fpga/1995 FPGA https://doi.org/10.1145/201310.201322 db/conf/fpga/fpga95.html#CongH95 Jason Cong Yuzheng Ding On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. 82-88 1995 conf/fpga/1995 FPGA https://doi.org/10.1145/201310.201324 db/conf/fpga/fpga95.html#CongD95 Jason Cong Andrew B. Kahng Cheng-Kok Koh Chung-Wen Albert Tsao Bounded-skew clock and Steiner routing under Elmore delay. 66-71 1995 conf/iccad/1995 ICCAD https://doi.org/10.1109/ICCAD.1995.479993 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.479993 https://dl.acm.org/citation.cfm?id=224861 db/conf/iccad/iccad1995.html#CongKKT95 Jason Cong Lei He 0001 Optimal wiresizing for interconnects with multiple sources. 568-574 1995 conf/iccad/1995 ICCAD https://doi.org/10.1109/ICCAD.1995.480173 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.480173 https://dl.acm.org/citation.cfm?id=225116 db/conf/iccad/iccad1995.html#CongH95 Jason Cong Patrick H. Madden Performance Driven Routing with Mulitiple Sources. 203-206 1995 conf/iscas/1995 ISCAS db/conf/iscas/iscas1995-1.html#CongM95 https://doi.org/10.1109/ISCAS.1995.521486 Jason Cong Cheng-Kok Koh Minimum-Cost Bounded-Skew Clock Routing. 215-218 1995 conf/iscas/1995 ISCAS db/conf/iscas/iscas1995-1.html#CongK95 https://doi.org/10.1109/ISCAS.1995.521489

Jason Cong Yuzheng Ding Tong Gao Kuang-Chien Chen LUT-based FPGA technology mapping under arbitrary net-delay models. 507-516 1994 18 Comput. Graph. 4 https://doi.org/10.1016/0097-8493(94)90063-9 db/journals/cg/cg18.html#CongDGC94

Jason Cong Yuzheng Ding On nominal delay minimization in LUT-based FPGA technology mapping. 73-94 1994 18 Integr. 1 https://doi.org/10.1016/0167-9260(94)90012-4 db/journals/integration/integration18.html#CongD94

Jason Cong Yuzheng Ding FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. 1-12 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.273754 db/journals/tcad/tcad13.html#CongD94

Jason Cong Yuzheng Ding On area/depth trade-off in LUT-based FPGA technology mapping. 137-148 1994 2 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.285741 db/journals/tvlsi/tvlsi2.html#CongD94

Jason Cong Cheng-Kok Koh Simultaneous driver and wire sizing for performance and power optimization. 408-425 1994 2 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/92.335010 db/journals/tvlsi/tvlsi2.html#CongK94

Charles J. Alpert Jason Cong Andrew B. Kahng Gabriel Robins Majid Sarrafzadeh On the Minimum Density Interconnection Tree Problem. 157-169 1994 2 VLSI Design 2 https://doi.org/10.1155/1994/20983 db/journals/vlsi/vlsi2.html#AlpertCKRS94

Yang Cai 0003 D. F. Wong 0001 Jason Cong Channel Density Minimization by Pin Permutation. 171-183 1994 2 VLSI Design 2 https://doi.org/10.1155/1994/68279 db/journals/vlsi/vlsi2.html#00030C94

Jason Cong Zheng Li Rajive L. Bagrodia Acyclic Multi-Way Partitioning of Boolean Networks. 670-675 1994 conf/dac/1994 DAC https://doi.org/10.1145/196244.196609 db/conf/dac/dac94.html#CongLB94 Jason Cong Wilburt Labio Narayanan Shivakumar Multi-way VLSI circuit partitioning based on dual net representation. 56-62 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629744 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629744 https://dl.acm.org/citation.cfm?id=191357 db/conf/iccad/iccad1994.html#CongLS94 Jason Cong Cheng-Kok Koh Simultaneous driver and wire sizing for performance and power optimization. 206-212 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629767 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629767 https://dl.acm.org/citation.cfm?id=191409 db/conf/iccad/iccad1994.html#CongK94 Rajive L. Bagrodia Zheng Li Vikas Jha Yuan Chen Jason Cong Parallel logic level simulation of VLSI circuits. 1354-1361 1994 conf/wsc/1994 WSC https://doi.org/10.1109/WSC.1994.717530 http://dl.acm.org/citation.cfm?id=194893 db/conf/wsc/wsc1994.html#BagrodiaLJCC94

Jason Cong Moazzem Hossain Naveed A. Sherwani A provably good multilayer topological planar routing algorithm in IC layout designs. 70-78 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.184844 db/journals/tcad/tcad12.html#CongHS93

Jason Cong Bryan Preas C. L. Liu 0001 Physical models and efficient algorithms for over-the-cell routing in standard cell design. 723-734 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.277618 db/journals/tcad/tcad12.html#CongPL93

Jason Cong Andrew B. Kahng Gabriel Robins Matching-based methods for high-performance clock routing. 1157-1169 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/43.238608 db/journals/tcad/tcad12.html#CongKR93

Jason Cong Yuzheng Ding On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. 213-218 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164675 db/conf/dac/dac93.html#CongD93 Kei-Yong Khoo Jason Cong An Efficient Multilayer MCM Router Based on Four-Via Routing. 590-595 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.165059 db/conf/dac/dac93.html#KhooC93 Jason Cong Kwok-Shing Leung Dian Zhou Performance-Driven Interconnect Design Based on Distributed RC Delay Model. 606-611 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.165065 db/conf/dac/dac93.html#CongLZ93 Jason Cong M'Lissa Smith A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. 755-760 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.165119 https://www.wikidata.org/entity/Q56335594 db/conf/dac/dac93.html#CongS93 Jason Cong Yuzheng Ding Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. 110-114 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580040 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580040 https://dl.acm.org/citation.cfm?id=259813 db/conf/iccad/iccad1993.html#CongD93 Jason Cong Kwok-Shing Leung Optimal wiresizing under the distributed Elmore delay model. 634-639 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580152 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580152 https://dl.acm.org/citation.cfm?id=259893 db/conf/iccad/iccad1993.html#CongL93 Charles J. Alpert Jason Cong Andrew B. Kahng Gabriel Robins Majid Sarrafzadeh Minimum Density Interconneciton Trees. 1865-1868 1993 conf/iscas/1993 ISCAS db/conf/iscas/iscas1993-3.html#AlpertCKRS93 Dian Zhou S. Su F. Tsui D. S. Gao Jason Cong A Two-pole Circuit Model for VLSI High-speed Interconnection. 2129-2132 1993 conf/iscas/1993 ISCAS db/conf/iscas/iscas1993-3.html#ZhouSTGC93 Jason Cong Moazzem Hossain Naveed A. Sherwani A Provably Good Algorithm for <i>k</i>-Layer Topological Planar Routing Problems. 113 1993 conf/vlsid/1993 VLSI Design db/conf/vlsid/vlsid1993.html#CongHS93 https://doi.org/10.1109/ICVD.1993.669658 https://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669658

Kuang-Chien Chen Jason Cong Yuzheng Ding Andrew B. Kahng Peter Trajmar DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. 7-20 1992 9 IEEE Des. Test Comput. 3 https://doi.org/10.1109/54.156154 http://doi.ieeecomputersociety.org/10.1109/54.156154 db/journals/dt/dt9.html#ChenCDKT92

Jason Cong Bryan Preas A new algorithm for standard cell global routing. 49-65 1992 14 Integr. 1 https://doi.org/10.1016/0167-9260(92)90010-V db/journals/integration/integration14.html#CongP92

Jason Cong Andrew B. Kahng Gabriel Robins Majid Sarrafzadeh Chak-Kuen Wong Provably good performance-driven global routing. 739-752 1992 11 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.137519 db/journals/tcad/tcad11.html#CongKRSW92

Jason Cong Lars W. Hagen Andrew B. Kahng Net Partitions Yield Better Module Partitions. 47-52 1992 conf/dac/1992 DAC http://portal.acm.org/citation.cfm?id=113938.110434 db/conf/dac/dac92.html#CongHK92 Kuang-Chien Chen Jason Cong Maximal reduction of lookup-table based FPGAs. 224-229 1992 EURO-DAC https://doi.org/10.1109/EURDAC.1992.246239 http://dl.acm.org/citation.cfm?id=161755 conf/eurodac/1992 db/conf/eurodac/euro-dac1992.html#ChenC92 Kei-Yong Khoo Jason Cong A fast multilayer general area router for MCM designs. 292-297 1992 EURO-DAC https://doi.org/10.1109/EURDAC.1992.246229 http://dl.acm.org/citation.cfm?id=161766 conf/eurodac/1992 db/conf/eurodac/euro-dac1992.html#KhooC92 Jason Cong Yuzheng Ding An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. 48-53 1992 conf/iccad/1992 ICCAD https://doi.org/10.1109/ICCAD.1992.279398 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1992.279398 https://dl.acm.org/citation.cfm?id=304055 db/conf/iccad/iccad1992.html#CongD92 Jason Cong Yuzheng Ding Andrew B. Kahng Peter Trajmar Kuang-Chien Chen An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. 154-158 1992 conf/iccd/1992 ICCD db/conf/iccd/iccd1992.html#CongDKTC92 https://doi.org/10.1109/ICCD.1992.276239 https://doi.ieeecomputersociety.org/10.1109/ICCD.1992.276239

Khe-Sing The Martin D. F. Wong Jason Cong A layout modification approach to via minimization. 536-541 1991 10 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.75637 db/journals/tcad/tcad10.html#TheWC91

Jason Cong C. L. Liu 0001 On the k-layer planar subset and topological via minimization problems. 972-981 1991 10 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/43.85735 db/journals/tcad/tcad10.html#CongL91

Jason Cong Pin assignment with global routing for general cell designs. 1401-1412 1991 10 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/43.97619 db/journals/tcad/tcad10.html#Cong91

Andrew B. Kahng Jason Cong Gabriel Robins High-Performance Clock Routing Based on Recursive Geometric Aatching. 322-327 1991 conf/dac/1991 DAC https://doi.org/10.1145/127601.127688 db/conf/dac/dac91.html#KahngCR91 Jason Cong Andrew B. Kahng Gabriel Robins Majid Sarrafzadeh C. K. Wong Performance-Driven Global Routing for Cell Based ICs. 170-173 1991 conf/iccd/1991 ICCD db/conf/iccd/iccd1991.html#CongKRSW91 https://doi.org/10.1109/ICCD.1991.139874 https://doi.ieeecomputersociety.org/10.1109/ICCD.1991.139874 Jason Cong Kei-Yong Khoo A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. 319-322 1991 conf/iccd/1991 ICCD db/conf/iccd/iccd1991.html#CongK91 https://doi.org/10.1109/ICCD.1991.139907 https://doi.ieeecomputersociety.org/10.1109/ICCD.1991.139907

Jason Cong C. L. Liu 0001 Over-the-cell channel routing. 408-418 1990 9 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.45872 db/journals/tcad/tcad9.html#CongL90

Jason Cong Bryan Preas C. L. Liu 0001 General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. 709-715 1990 conf/dac/1990 DAC https://doi.org/10.1145/123186.123448 db/conf/dac/dac90.html#CongPL90 Jason Cong C. L. Liu 0001 On the k-layer planar subset and via minimization problems. 459-463 1990 EURO-DAC https://doi.org/10.1109/EDAC.1990.136691 http://dl.acm.org/citation.cfm?id=950073 conf/eurodac/1990 db/conf/eurodac/euro-dac1990.html#CongL90 Khe-Sing The D. F. Wong 0001 Jason Cong VIA Minimization by Layout Modification. 799-802 1989 conf/dac/1989 DAC https://doi.org/10.1145/74382.74533 db/conf/dac/dac89.html#TheWC89 Jason Cong Pin assignment with global routing. 302-305 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76958 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76958 conf/iccad/1989 db/conf/iccad/iccad1989.html#Cong89 Sai-keung Dong Jason Cong C. L. Liu 0001 Constrained floorplan design for flexible blocks. 488-491 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76997 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76997 conf/iccad/1989 db/conf/iccad/iccad1989.html#DongCL89

Jason Cong Martin D. F. Wong C. L. Liu 0001 A new approach to three- or four-layer channel routing. 1094-1104 1988 7 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/43.7808 db/journals/tcad/tcad7.html#CongWL88

Nany Hasan Jason Cong C. L. Liu 0001 A new formulation of yield enhancement problems for reconfigurable chips. 520-523 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122562 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122562 conf/iccad/1988 db/conf/iccad/iccad1988.html#HasanCL88 Stefan Abi-Karam Umut A. Acar Michael Adler Amit Agarwal Vaibhav Aggarwal Daniel Aharoni Afzal Ahmad Robert C. Aitken Masood Akram Charles J. Alpert José AlvarezJose Alvarez Anima Anandkumar Rajive L. Bagrodia Yunsheng Bai Justas Balcas Nicholas Bambos Taesik Bang Joseph A. Bannister Akhil Raj Baranwal Ahmad Sedigh Baroughi Clark W. Barrett Alberto A. Del Barrio Suhail Basalama Lotfi Benmohamed Larry Bergman Vaughn Betz Nikolaj S. Bjørner David T. Blaauw Garrett J. Blair Hugh T. Blair Michaela Blott Dolev Bluvstein Ivo Bolsens Robert K. Brayton Zoran Budimlic Alex A. T. Bui Jeff Burns Gyungsu Byun Yang Cai 0003 Madelyn Cain Chengdi Cao Le Cao Yingqi Cao Luca P. Carloni Gert Cauwenberghs Samarjit Chakraborty Tony F. Chan Chin-Chih Chang Mau-Chung Frank ChangM.-C. Frank ChangM. Frank Chang Shih-Chieh Chang 0001 Saranyu Chattopadhyay Deming Chen Gang Chen 0020 Huan-Neng Ron Chen Jiahua Chen Jianwen Chen Kuang-Chien Chen Shu Chen Xi Chen 0107 Yao Chen 0008 Ying Chen Yiran Chen 0001 Youxiang Chen Yuan Chen Yuting Chen 0003Yu-Ting Chen 0003 Zhe Chen 0030 Kwang-Ting Cheng Xu Cheng 0001 Yuze Chi Derek Chiou Wei-Han Cho Chris Choi Hanjun Choi Young-kyu ChoiYoung Kyu Choi Jerry M. Chow Tyson Condie Olivier Coudert Can Cui Xiuping Cui Tri Dao Adnan Darwiche André DeHon Haoran Deng Kristof Denolf Nitin Deo Yuzheng Ding Zijian Ding Antun Domic Chen Dong 0003 Hongwei Dong Sai-keung Dong Sheqin Dong Fred Douglis Jieqiong Du Linfeng Du Yuan Du Yubo Du Pradeep Dubey Henry Duwe Lieven Eeckhout Milos D. Ercegovac Chengyu Fan Yiping Fan Jie Fang Zhenman Fang Paul D. Franzon Nicholas Fraser Eli Gafni Vijay Ganesh 0001 D. S. Gao Min Gao 0003 Ruipeng Gao Tong Gao Wen Gao 0001 Moshe Gavrielov Jinming Ge Nithin George Mario Gerla Mohammad Ali Ghodrat Michael Gill Peyman Golshani Jian Gong Kailash Gopalakrishnan Satoshi Goto Beayna Grigorian Max Grossman Aditya Grover Jiaqi Gu 0002 Naiqing Guan Yijin Guan Muhammad Ali Gulzar Changliang Guo Chuanxiong Guo Licheng Guo Bhusan Gupta Hersh Gupta Puneet Gupta 0001 Swathi T. Gurumani Karthik Gururaj Adriana E. Gutierrez Lars W. Hagen Guoling Han Kaiqiao Han Song Han 0003 Callie Hao Yuchen Hao Eshel Haritan Randy Harr Nany Hasan Lei He 0001 Tong He Zifan He Gernot Heiser Román Hermida Richard Ho James C. Hoe Xianlong Hong Moazzem Hossain Zhenyu Hou Andrew Howe Cheng-Tao Hsieh Cho-Jui Hsieh Hsieh-Hung Hsieh William Hsu Boyu Hu Han Hu Jingtong Hu Xiaobo Sharon HuX. Sharon Hu Yao Hu Yuwei Hu Ziniu Hu Anpeng Huang Hui Huang 0001 Muhuan Huang Po-Tsang Huang Rulin Huang Yuhui Huang Zhangqin Huang Zhijun Huang Zijie Huang 0002 Christopher J. Hughes Eddie Hung Yean-Yow Hwang Wen-Mei W. HwuWen-mei W. Hwu Matteo Interlandi Catalin Iordache Jeremy Ir Tatsuo Itoh Ashok Jagannathan Sushil Jajodia Farnoosh Javadi Vikas Jha Shixin Ji Huizhu Jia Liancheng Jia Yunshan Jia Ming Jiang 0001 Song Jiang 0001 Wei Jiang 0035 Alex K. Jones Siddharth Joshi 0001 Chewnpu Jou William H. Joyner Gregory Jun Chaehyun Jung Andrew B. Kahng Adam Kaplan Sinan Kaptanoglu Ramesh Karri Alireza Kaviani Huifeng Ke Jake Ke Moazin Khatti Kei-Yong Khoo Hassan Kianinejad Hoshik Kim Jeonghun Kim Jongsun Kim Miryung Kim Yanghyo Kim Yanghyo Rod Kim Jason Kimko Darko Kirovski Aron Kirschen Leonard Kleinrock Tim Kogel Cheng-Kok Koh Tianming Kong Tim Kong Kris Konigsfeld Christoforos E. KozyrakisChristos Kozyrakis Stan Krolikoski Rakesh Kumar 0002 Chun-Liang Kuo Dylan Kupsh Eren Kurshan Eren Kursun Wilburt Labio Chunbo Lai Yi-Hsiang Lai Jason Lau Chris Lavin Yann LeCun John Lee 0002 Ruby B. Lee Suk-Bok Lee Serge Leef Jie Lei 0001 Kwok-Shing Leung Bojie Li Chen Li 0004 Fei Li 0003 Hai Li 0001Hai Helen Li Honching Li Honching Peter Li Jiajie Li Meng Li 0016 Peng Li 0031 Ruoyan Li Sen Li Shuo Li 0007 Weikai Li 0002 Wuxi Li Xiaoguang Li Xiaoming Li 0001 Xin Li Xingchen Li Xiuhong Li Yunsong Li 0001 Zheng Li Zhinan Li Zhuoyuan Li 0003 Faming Liang Hao Liang 0003 Jiawei Liang Rongjian Liang Yun Liang 0001 Kevin Lim Sung Kyu Lim Joey Y. Lin Shiding Lin Wan-Hsuan Lin Yan Lin 0001 Yingyan (Celine) LinYingyan Celine LinYingyan Lin 0001 Yizhou Lin Michael L. Littman Albert Liu Bin Liu 0006 C. L. Liu 0001 Chunyue Liu Gai Liu Jie Liu 0072 Jiuyang Liu Jun S. Liu Pengyu Liu Ran Liu 0010 Sihao Liu Xianhua Liu 0001 Yilian Liu Yong Liu Yongxiang Liu Yuezhou Liu Jack Lo Michael Lo John Lockwood Wangning Long Florian Lonsing Philip Lopresti Anni Lu Liqiang Lu Songwu Lu Robert F. Lucas Mikhail D. Lukin Guojie Luo Zizhang Luo Chiyuan Ma Rui Ma Tony Ma Yuchun Ma Peter MaassPeter Maaß Patrick H. Madden Gabrielle Magat Pongstorn Maidee Rupak Majumdar Sharad Malik Rishabh Mani Dinesh Manocha Dan Mansur Diana Marculescu Karl Marrett Edward J. McCluskey Bradley D. McCredie Joseph Melber Giovanni De Micheli Dan Milliron Dejan S. Milojicic Kirill Minkovich Azalia Mirhoseini Baharan Mirzasoleiman Subhasish Mitra Mosur Mohan Paolo Montuschi Phil Moorby Keivan Moradi Hyun-Seung Mun Faruk V. Mutlu N. S. Nagaraj Mishali Naik Farid N. Najm Gi-Joon Nam Lan Nan Sumit Nanda Gabriele Nataneli Stephen Neuendorffer Harvey B. Newman Tan Nguyen Tung Nguyen Murphy Yuezhen Niu Juanjo Noguera David Noice Tony Nowatzki Jihun Oh Takumi Okamoto Kunle Olukotun Jian Ouyang Thomas Page David Z. PanDavid Zhigang Pan Peichen Pan Z. D. Pan Wesley Pang Alexandros Papakonstantinou Chris Sin Park Hyunseok Park Jongchan Park John Peck Ioannis Pefkianakis Tomás F. Pena Chi-Chen Peng Chunyi Peng 0001 Davide Pesavento Luca Piccolboni Shuohao Ping Sumukh Pinge Wolfgang Porod Miodrag Potkonjak Louis-Noël Pouchet Stéphane Pouget Raghu Prabhakar Neha Prakriya Bryan Preas Jagannath Premkumar Isabelle Puaut Ruchir Puri Weikang Qiao Zongyue Qin Jan M. Rabaey Eric Radke Riko Radojcic Priyanka Raina Glenn ReinmanGlenn D. Reinman Haoxing Ren Mark Ren Christopher B. Reynolds Peter Rickert David Roazen Gabriel Robins Ramón M. Rodríguez-Dagnino Martin Roettler Luis Romero Michail RomesisMichalis Romesis Hongbo Rong Wolfgang Rosenstiel Tajana Rosing Dan Roth Chris Rowen Zhenyuan Ruan Mitchell Rudd Kyle Rupnow Krzysztof Rutkowski P. Sadayappan Nikola Samardzic Hanan Samet John Sanguinetti Carlos Santillana Rishov Sarkar Vivek Sarkar Majid Sarrafzadeh Alina Simion Sbîrlea Michael Schulte Donatella Sciuto Naresh R. Shanbhag Megan Shand Susmit Shannigrahi Sophia Shao John Shen Li Shen Shiwen Shen Yujia Shen Jiayi Sheng Kenneth L. Shepard Naveed A. Sherwani Junxiao Shi Shaoshuai Shi Yidan Shi Yiyu Shi 0001 Toshiyuki Shibuya Joseph R. Shinnerl Nagesh Shirali Narayanan Shivakumar Ray Simar Jr.Ray Simar Aarti Singh Eshan Singh Raimondas Sirvinskas Aishwarya Sivaraman M'Lissa Smith Eran Socher Atefeh Sohrabizadeh Linghao Song Sichen Song Deepraj Soni Prasanna V. Srinivas Yannick Stade Hans Stork Maxwell Strange John A. Stratton Mike Strickland Chunyou Su S. Su Brendan Sullivan Guangyu Sun 0003 Jiayu Sun Renliang Sun Yizhou Sun Kenton Sze Brian Tagiku Endri Taka Andrés Takach Sai-Wang Tam Yuval Tamir Bochen TanDaniel Bochen Tan Mingxing Tan Adrian Tang 0002 Alexander K. Taylor 0002Alexander Taylor 0002 Steve Teig Khe-Sing The Kanit Therdsteerasukdi Thorlindur Thorolfsson Xingyu Tian Sankalpa Timilsina Chenyi Tong Peter Trajmar Caroline Trippel Anderson Truong Chung-Wen Albert Tsao Kalliopi Tsota F. Tsui Taku Uchino Ecenur Ustun Lieven Vandenberghe Pranathi Vasireddy Massimiliano Di Ventra Luminita A. Vese Yan Zhang VI John D. Villasenor Kees A. Vissers Marco Vitanza Kazutoshi Wakabayashi Cheng Wan 0005 Lu Wan Chengyue Wang 0002 Chi Wang 0001 Ding Wang Haixin Wang 0003 Hanrui Wang 0002 Hanyu Wang Jie Wang 0022 Kan Wang 0003 Libo Wang Maogang Wang Pei Wang Peng Wang 0025 Sheng-Tao Wang Tao Wang 0004 Wei Wang 0010 Wenqiang Wang Xiaoxuan Wang Xiaoyang Wang 0006 Yang Wang Yewen Wang Yi-Chu Wang Yu Wang 0002 Yusu Wang Yuxin Wang Yuyue Wang 0001 Zhengrong Wang Faaiq Waqar Faaiq G. Waqar Yoshi Watanabe Jie Wei Peng Wei 0004 Xuechao Wei Jian Weng 0002 Kathleen Wijaya Robert Wille Marilyn WolfWayne H. Wolf Chak-Kuen WongC. K. Wong H.-S. Philip Wong Martin D. F. WongD. F. Wong 0001 Wing Hung Wong Chang Wu Di Wu 0010 Hao Wu 0026 Haoyang Wu P.-Y. Wu Xinrui Wu Yingquan Wu Yuanhao Wu Shaojie Xiang Bingjun Xiao Chunhua Xiao Nong Xiao 0001 Yuanlong Xiao Linzhen Xie Min Xie 0004 Xiaodong Xie Xinfeng Xie Yuan Xie 0001 Yutong Xie 0011 Jinjun Xiong Dongmin Xu Jingxian Xu Junjuan Xu Ningyi Xu Songjie Xu Wenyao Xu Qing Xue Kenneth Yan Ming Yan 0006 Hannah Honghua Yang Liqiong Yang X. William Yang Xun Yang Yu Yang 0007 Zhuoping Yang Fan Ye 0003 Hanchen Ye Shengyu Ye Edmund M. YehEdmund Yeh Jui-Nan Yen Steve H.-C. Yen Jianwei Yin Jieming Yin Sungyeal Yoon Cliff Young Cody Hao Yu Shimeng Yu Tianhe Yu Bo Yuan Xin Yuan 0005 Zhihang Yuan Behrooz Zahiri Chen Zhang 0001 Han Zhang Jiahao Zhang Jiaxi Zhang 0001 Jiyu Zhang Lixia Zhang 0001 Lucheng Zhang Peng Zhang 0007 Qian Zhang 0020 Shaochong Zhang Shichang Zhang Tao Zhang 0032 Tianqi Zhang Wei Zhang 0012 Weihao Zhang Wentai Zhang 0001 Xiaofan Zhang 0001 Yan Zhang Youhui Zhang Zhiru Zhang Size Zheng 0001 Su Zheng Shunan Zhong Dian Zhou Jim Zhou Peipei Zhou 0001 Qiang Zhou 0001 Sheng Zhou Yuan Zhou Yun Zhou Chuang Zhu Muye Zhu Yanqiao Zhu 0001 Jinming Zhuang Maxim Zhulin Brian Zingg Leqi Zou Yang Zou 0001 Yi Zou Wei Zuo