28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications.

Ching-Te Chuang Huan-Jan Tseng Po-Tsang Huang Shang-Lin Wu Sheng-Chi Lung Wei-Chang Wang Wei Hwang Ching-Te Chuang 28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. 248-253 2019 SoCC https://doi.org/10.1109/SOCC46988.2019.1570555748 conf/socc/2019 db/conf/socc/socc2019.html#TsengHWLWHC19 Yun-Sheng Chan Po-Tsang Huang Shang-Lin Wu Sheng-Chi Lung Wei-Chang Wang Wei Hwang Ching-Te Chuang 0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. 272-277 2018 SoCC https://doi.org/10.1109/SOCC.2018.8618562 conf/socc/2018 db/conf/socc/socc2018.html#ChanHWLWHC18 Yi-Chun Wu Po-Tsang Huang Shang-Lin Wu Sheng-Chi Lung Wei-Chang Wang Wei Hwang Ching-Te Chuang 28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. 1-4 2018 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2018.8373255 conf/vlsi-dat/2018 db/conf/vlsi-dat/vlsi-dat2018.html#WuHWLWHC18

Yu-Chieh Huang Po-Tsang Huang Shang-Lin Wu Yu-Chen Hu Yan-Huei You Ming Chen Yan-Yu Huang Hsiao-Chun Chang Yen-Han Lin Jeng-Ren Duann Tzai-Wen Chiu Wei Hwang Kuan-Neng Chen Ching-Te Chuang Jin-Chern Chiou Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. 1013-1025 2017 11 IEEE Trans. Biomed. Circuits Syst. 5 https://doi.org/10.1109/TBCAS.2017.2669439 https://www.wikidata.org/entity/Q40458401 db/journals/tbcas/tbcas11.html#HuangHWHYCHCLDC17

Shang-Lin Wu Kuang-Yu Li Po-Tsang Huang Wei Hwang Ming-Hsien Tu Sheng-Chi Lung Wei-Sheng Peng Huan-Shun Huang Kuen-Di Lee Yung-Shin Kao Ching-Te Chuang A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. 1791-1802 2017 64-I IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2017.2681738 db/journals/tcas/tcasI64.html#WuLHHTLPHLKC17

Chia-Ning Chang Yin-Nien Chen Po-Tsang Huang Pin Su Ching-Te Chuang Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8051018 conf/iscas/2017 db/conf/iscas/iscas2017.html#ChangCHSC17 Po-Tsang Huang Yu-Chieh Huang Shang-Lin Wu Yu-Chen Hu Ming-Wei Lu Ting-Wei Sheng Fung-Kai Chang Chun-Pin Lin Nien-Shang Chang Hung-Lieh Chen Chi-Shi Chen Jeng-Ren Duann Tzai-Wen Chiu Wei Hwang Kuan-Neng Chen Ching-Te Chuang Jin-Chern Chiou An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050687 conf/iscas/2017 db/conf/iscas/iscas2017.html#HuangHWHLSCLCCC17

Shang-Lin Wu Chien-Yu Lu Ming-Hsien Tu Huan-Shun Huang Kuen-Di Lee Yung-Shin Kao Ching-Te Chuang A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. 89-98 2016 51 Microelectron. J. https://doi.org/10.1016/j.mejo.2016.02.011 db/journals/mj/mj51.html#WuLTHLKC16

Jian-Hao Wang Yin-Nien Chen Pin Su Ching-Te Chuang Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. 1-4 2016 ICICDT https://doi.org/10.1109/ICICDT.2016.7542057 conf/icicdt/2016 db/conf/icicdt/icicdt2016.html#WangCSC16 Yi-Wei Chiu Yu-Hao Hu Jun-Kai Zhao Shyh-Jye Jou Ching-Te Chuang A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. 1014-1017 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7527415 conf/iscas/2016 db/conf/iscas/iscas2016.html#ChiuHZJC16 Yu-Chieh Huang Po-Tsang Huang Shang-Lin Wu Yu-Chen Hu Yan-Huei You Ming Chen Yan-Yu Huang Hsiao-Chun Chang Yen-Han Lin Jeng-Ren Duann Tzai-Wen Chiu Wei Hwang Kuan-Neng Chen Ching-Te Chuang Jin-Chern Chiou An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. 1302-1305 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7527487 conf/iscas/2016 db/conf/iscas/iscas2016.html#HuangHWHYCHCLDC16 Vita Pi-Ho Hu Pin Su Ching-Te Chuang Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. 2106-2109 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7538995 conf/iscas/2016 db/conf/iscas/iscas2016.html#HuSC16 Chang-Hung Yu Pin Su Ching-Te Chuang Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. 242-247 2016 ISLPED https://doi.org/10.1145/2934583.2934630 https://www.wikidata.org/entity/Q130867544 conf/islped/2016 db/conf/islped/islped2016.html#YuSC16 Ming Chen Po-Tsang Huang Shang-Lin Wu Wei Hwang Ching-Te Chuang Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. 18-23 2016 SoCC https://doi.org/10.1109/SOCC.2016.7905425 conf/socc/2016 db/conf/socc/socc2016.html#ChenHWHC16

Chien-Yu Lu Ching-Te Chuang Shyh-Jye Jou Ming-Hsien Tu Ya-Ping Wu Chung-Ping Huang Paul-Sen Kan Huan-Shun Huang Kuen-Di Lee Yung-Shin Kao A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. 958-962 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2014.2318518 db/journals/tvlsi/tvlsi23.html#LuCJTWHKHLK15

Tse-Ching Wu Chien-Ju Chen Yin-Nien Chen Vita Pi-Ho Hu Pin Su Ching-Te Chuang Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. 1-4 2015 ICICDT https://doi.org/10.1109/ICICDT.2015.7165880 conf/icicdt/2015 db/conf/icicdt/icicdt2015.html#WuCCHSC15 Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. 601-604 2015 ISCAS https://doi.org/10.1109/ISCAS.2015.7168705 conf/iscas/2015 db/conf/iscas/iscas2015.html#HuFSC15 Chien-Ju Chen Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. 2325-2328 2015 ISCAS https://doi.org/10.1109/ISCAS.2015.7169149 conf/iscas/2015 db/conf/iscas/iscas2015.html#ChenCFHSC15 Chun-Ying Huang Po-Tsang Huang Chih-Chao Yang Ching-Te Chuang Wei Hwang Energy-efficient gas recognition system with event-driven power control. 245-250 2015 SoCC https://doi.org/10.1109/SOCC.2015.7406956 conf/socc/2015 db/conf/socc/socc2015.html#HuangHYCH15 Tse-Ching Wu Chien-Ju Chen Yin-Nien Chen Vita Pi-Ho Hu Pin Su Ching-Te Chuang Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. 339-344 2015 SoCC https://doi.org/10.1109/SOCC.2015.7406978 conf/socc/2015 db/conf/socc/socc2015.html#WuCCHSC15 Yi-Ping Kuo Po-Tsang Huang Chung-Shiang Wu Yu-Jie Liang Ching-Te Chuang Yuan-Hua Chu Wei Hwang All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. 1-4 2015 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2015.7114514 conf/vlsi-dat/2015 db/conf/vlsi-dat/vlsi-dat2015.html#KuoHWLCCH15 Chih-Chao Yang Po-Tsang Huang Chun-Ying Huang Ching-Te Chuang Wei Hwang Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. 1-4 2015 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2015.7114512 conf/vlsi-dat/2015 db/conf/vlsi-dat/vlsi-dat2015.html#YangHHCH15

Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. 389-399 2014 4 IEEE J. Emerg. Sel. Topics Circuits Syst. 4 https://doi.org/10.1109/JETCAS.2014.2361072 db/journals/esticas/esticas4.html#ChenFHSC14

Ming-Long Fan Shao-Yu Yang Vita Pi-Ho Hu Yin-Nien Chen Pin Su Ching-Te Chuang Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. 698-711 2014 54 Microelectron. Reliab. 4 https://doi.org/10.1016/j.microrel.2013.12.026 db/journals/mr/mr54.html#FanYHCSC14

Po-Tsang Huang Shang-Lin Wu Yu-Chieh Huang Lei-Chun Chou Teng-Chieh Huang Tang-Hsuan Wang Yu-Rou Lin Chuan-An Cheng Wen-Wei Shen Ching-Te Chuang Kuan-Neng Chen Jin-Chern Chiou Wei Hwang Ho-Ming Tong 2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. 810-823 2014 8 IEEE Trans. Biomed. Circuits Syst. 6 https://doi.org/10.1109/TBCAS.2014.2385061 https://www.wikidata.org/entity/Q40248789 db/journals/tbcas/tbcas8.html#HuangWHCHWLCSCCCHT14

Dao-Ping Wang Hon-Jarn Lin Ching-Te Chuang Wei Hwang Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. 188-192 2014 61-II IEEE Trans. Circuits Syst. II Express Briefs 3 https://doi.org/10.1109/TCSII.2013.2296137 db/journals/tcas/tcasII61.html#WangLCH14

Yi-Wei Chiu Yu-Hao Hu Ming-Hsien Tu Jun-Kai Zhao Yuan-Hua Chu Shyh-Jye Jou Ching-Te Chuang 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. 2578-2585 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 9 https://doi.org/10.1109/TCSI.2014.2332267 db/journals/tcas/tcasI61.html#ChiuHTZCJC14

Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. 3339-3347 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 12 https://doi.org/10.1109/TCSI.2014.2335032 db/journals/tcas/tcasI61.html#ChenFHSC14

Nan-Chun Lien Li-Wei Chu Chien-Hen Chen Hao-I Yang Ming-Hsien Tu Paul-Sen Kan Yong-Jyun Hu Ching-Te Chuang Shyh-Jye Jou Wei Hwang A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. 3416-3425 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 12 https://doi.org/10.1109/TCSI.2014.2336531 db/journals/tcas/tcasI61.html#LienCCYTKHCJH14

Po-Tsang Huang Shu-Lin Lai Ching-Te Chuang Wei Hwang Jason Huang Angelo Hu Paul Kan Michael Jia Kimi Lv Bright Zhang 0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. 129-132 2014 A-SSCC https://doi.org/10.1109/ASSCC.2014.7008877 conf/asscc/2014 db/conf/asscc/asscc2014.html#HuangLCHHHKJLZ14 Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. 1122-1125 2014 ISCAS https://doi.org/10.1109/ISCAS.2014.6865337 conf/iscas/2014 db/conf/iscas/iscas2014.html#HuFSC14 Ming-Long Fan Vita Pi-Ho Hu Yin-Nien Chen Pin Su Ching-Te Chuang Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. 1130-1133 2014 ISCAS https://doi.org/10.1109/ISCAS.2014.6865339 conf/iscas/2014 db/conf/iscas/iscas2014.html#FanHCSC14 Tang-Hsuan Wang Po-Tsang Huang Kuan-Neng Chen Jin-Chern Chiou Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Ching-Te Chuang Wei Hwang Energy-efficient configurable discrete wavelet transform for neural sensing applications. 1841-1844 2014 ISCAS https://doi.org/10.1109/ISCAS.2014.6865516 conf/iscas/2014 db/conf/iscas/iscas2014.html#WangHCCCCTCH14 Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. 255-258 2014 ISLPED https://doi.org/10.1145/2627369.2627649 conf/islped/2014 db/conf/islped/islped2014.html#ChenFHSC14 Po-Tsang Huang Lei-Chun Chou Teng-Chieh Huang Shang-Lin Wu Tang-Shuan Wang Yu-Rou Lin Chuan-An Cheng Wen-Wei Shen Kuan-Neng Chen Jin-Chern Chiou Ching-Te Chuang Wei Hwang Kuo-Hua Chen Chi-Tsung Chiu Ming-Hsiang Cheng Yueh-Lung Lin Ho-Ming Tong 18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. 320-321 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757452 conf/isscc/2014 db/conf/isscc/isscc2014.html#HuangCHWWLCSCCC14 Pei-Chen Wu Yi-Ping Kuo Chung-Shiang Wu Ching-Te Chuang Yuan-Hua Chu Wei Hwang PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. 136-139 2014 SoCC https://doi.org/10.1109/SOCC.2014.6948914 conf/socc/2014 db/conf/socc/socc2014.html#WuKWCCH14 Chao-Kuei Chung Chien-Yu Lu Zhi-Hao Chang Shyh-Jye Jou Ching-Te Chuang Ming-Hsien Tu Yu-Hsian Chen Yong-Jyun Hu Paul-Sen Kan Huan-Shun Huang Kuen-Di Lee Yung-Shin Kao A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. 455-462 2014 SoCC https://doi.org/10.1109/SOCC.2014.6948972 conf/socc/2014 db/conf/socc/socc2014.html#ChungLCJCTCHKHLK14 Shang-Lin Wu Po-Tsang Huang Teng-Chieh Huang Kuan-Neng Chen Jin-Chern Chiou Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Ching-Te Chuang Wei Hwang Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. 1-4 2014 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2014.6834893 conf/vlsi-dat/2014 db/conf/vlsi-dat/vlsi-dat2014.html#WuHHCCCCTCH14

Amlan Ghosh Rahul M. Rao Jae-Joon Kim Ching-Te Chuang Richard B. Brown Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. 1683-1692 2013 21 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2012.2218838 db/journals/tvlsi/tvlsi21.html#GhoshRKCB13

Yan-Pin Huang Ruoh-Ning Tzeng Yu-San Chien Ming-Shaw Shy Teu-Hua Lin Kuo-Hua Chen Ching-Te Chuang Wei Hwang Chi-Tsung Chiu Ho-Ming Tong Kuan-Neng Chen Low temperature (<180 °C) bonding for 3D integration. 1-5 2013 3DIC https://doi.org/10.1109/3DIC.2013.6702319 conf/3dic/2013 db/conf/3dic/3dic2013.html#HuangTCSLCCHCTC13 Teng-Chieh Huang Po-Tsang Huang Shang-Lin Wu Kuan-Neng Chen Jin-Chern Chiou Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Ching-Te Chuang Wei Hwang Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. 238-241 2013 BioCAS https://doi.org/10.1109/BioCAS.2013.6679683 conf/biocas/2013 db/conf/biocas/biocas2013.html#HuangHWCCCCTCH13 Shao-Yu Yang Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. 61-64 2013 ICICDT https://doi.org/10.1109/ICICDT.2013.6563303 conf/icicdt/2013 db/conf/icicdt/icicdt2013.html#YangCFHSC13 Ming-Hung Chang Shang-Yuan Lin Pei-Chen Wu Olesya Zakoretska Ching-Te Chuang Kuan-Neng Chen Chen-Chao Wang Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Wei Hwang Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. 133-136 2013 ISCAS https://doi.org/10.1109/ISCAS.2013.6571800 conf/iscas/2013 db/conf/iscas/iscas2013.html#ChangLWZCCWCCTH13 Chi-Shin Chang Hao-I Yang Wei-Nan Liao Yi-Wei Lin Nan-Chun Lien Chien-Hen Chen Ching-Te Chuang Wei Hwang Shyh-Jye Jou Ming-Hsien Tu Huan-Shun Huang Yong-Jyun Hu Paul-Sen Kan Cheng-Yo Cheng Wei-Chang Wang Jian-Hao Wang Kuen-Di Lee Chia-Cheng Chen Wei-Chiang Shih A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. 1468-1471 2013 ISCAS https://doi.org/10.1109/ISCAS.2013.6572134 conf/iscas/2013 db/conf/iscas/iscas2013.html#ChangYLLLCCHJTHHKCWWLCS13 Yi-Wei Chiu Yu-Hao Hu Ming-Hsien Tu Jun-Kai Zhao Shyh-Jye Jou Ching-Te Chuang A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. 51-56 2013 ISLPED https://doi.org/10.1109/ISLPED.2013.6629266 http://dl.acm.org/citation.cfm?id=2648683 conf/islped/2013 db/conf/islped/islped2013.html#ChiuHTZJC13 Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. 347-352 2013 ISQED https://doi.org/10.1109/ISQED.2013.6523633 conf/isqed/2013 db/conf/isqed/isqed2013.html#HuFSC13 Chih-Wei Chang Po-Tsang Huang Lei-Chun Chou Shang-Lin Wu Shih-Wei Lee Ching-Te Chuang Kuan-Neng Chen Jin-Chern Chiou Wei Hwang Yen-Chi Lee Chung-Hsi Wu Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Through-silicon-via-based double-side integrated microsystem for neural sensing applications. 102-103 2013 ISSCC https://doi.org/10.1109/ISSCC.2013.6487655 conf/isscc/2013 db/conf/isscc/isscc2013.html#ChangHCWLCCCHLWCCT13 Nan-Chun Lien Ching-Te Chuang Wen-Rong Wu Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. 105-109 2013 SoCC https://doi.org/10.1109/SOCC.2013.6749669 conf/socc/2013 db/conf/socc/socc2013.html#LienCW13 Wei-Nan Liao Nan-Chun Lien Chi-Shin Chang Li-Wei Chu Hao-I Yang Ching-Te Chuang Shyh-Jye Jou Wei Hwang Ming-Hsien Tu Huan-Shun Huang Jian-Hao Wang Paul-Sen Kan Yong-Jyun Hu A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. 110-115 2013 SoCC https://doi.org/10.1109/SOCC.2013.6749670 conf/socc/2013 db/conf/socc/socc2013.html#LiaoLCCYCJHTHWKH13 Chien-Yu Lu Ching-Te Chuang A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance. 325-329 2013 SoCC https://doi.org/10.1109/SOCC.2013.6749710 conf/socc/2013 db/conf/socc/socc2013.html#LuC13

Ming-Hsien Tu Jihi-Yu Lin Ming-Chien Tsai Chien-Yu Lu Yuh-Jiun Lin Meng-Hsueh Wang Huan-Shun Huang Kuen-Di Lee Wei-Chiang Shih Shyh-Jye Jou Ching-Te Chuang A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. 1469-1482 2012 47 IEEE J. Solid State Circuits 6 https://doi.org/10.1109/JSSC.2012.2187474 db/journals/jssc/jssc47.html#TuLTLLWHLSJC12

Chien-Yu Lu Ming-Hsien Tu Hao-I Yang Ya-Ping Wu Huan-Shun Huang Yuh-Jiun Lin Kuen-Di Lee Yung-Shin Kao Ching-Te Chuang Shyh-Jye Jou Wei Hwang A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. 863-867 2012 59-II IEEE Trans. Circuits Syst. II Express Briefs 12 https://doi.org/10.1109/TCSII.2012.2231017 db/journals/tcas/tcasII59.html#LuTYWHLLKCJH12

Ming-Long Fan Vita Pi-Ho Hu Yin-Nien Chen Pin Su Ching-Te Chuang Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. 878-882 2012 59-II IEEE Trans. Circuits Syst. II Express Briefs 12 https://doi.org/10.1109/TCSII.2012.2231016 db/journals/tcas/tcasII59.html#FanHCSC12

Chien-Yu Hsieh Ming-Long Fan Vita Pi-Ho Hu Pin Su Ching-Te Chuang Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. 1201-1210 2012 20 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2011.2156435 db/journals/tvlsi/tvlsi20.html#HsiehFHSC12

Shao-Cheng Wang Geng-Cing Lin Yi-Wei Lin Ming-Chien Tsai Yi-Wei Chiu Shyh-Jye Jou Ching-Te Chuang Nan-Chun Lien Wei-Chiang Shih Kuen-Di Lee Jyun-Kai Chu Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. 116-119 2012 APCCAS https://doi.org/10.1109/APCCAS.2012.6418985 conf/apccas/2012 db/conf/apccas/apccas2012.html#WangLLTCJCLSLC12 Chia-Hao Pao Ming-Long Fan Ming-Fu Tsai Yin-Nien Chen Vita Pi-Ho Hu Pin Su Ching-Te Chuang A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. 463-466 2012 APCCAS https://doi.org/10.1109/APCCAS.2012.6419072 conf/apccas/2012 db/conf/apccas/apccas2012.html#PaoFTCHSC12 Ming-Fu Tsai Jen-Huan Tsai Ming-Long Fan Pin Su Ching-Te Chuang Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. 471-474 2012 APCCAS https://doi.org/10.1109/APCCAS.2012.6419074 conf/apccas/2012 db/conf/apccas/apccas2012.html#TsaiTFSC12 Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. 77-80 2012 ESSDERC https://doi.org/10.1109/ESSDERC.2012.6343337 conf/essderc/2012 db/conf/essderc/essderc2012.html#HuFSC12 Yin-Nien Chen Ming-Long Fan Vita Pi-Ho Hu Ming-Fu Tsai Chia-Hao Pao Pin Su Ching-Te Chuang A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. 157-160 2012 ESSDERC https://doi.org/10.1109/ESSDERC.2012.6343357 conf/essderc/2012 db/conf/essderc/essderc2012.html#ChenFHTPSC12 Chia-Hao Pao Ming-Long Fan Ming-Fu Tsai Yin-Nien Chen Vita Pi-Ho Hu Pin Su Ching-Te Chuang Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. 1-4 2012 ICICDT https://doi.org/10.1109/ICICDT.2012.6232841 conf/icicdt/2012 db/conf/icicdt/icicdt2012.html#PaoFTCHSC12 Hao-I Yang Yi-Wei Lin Mao-Chih Hsia Geng-Cing Lin Chi-Shin Chang Yin-Nien Chen Ching-Te Chuang Wei Hwang Shyh-Jye Jou Nan-Chun Lien Hung-Yu Li Kuen-Di Lee Wei-Chiang Shih Ya-Ping Wu Wen-Ta Lee Chih-Chiang Hsu High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. 1831-1834 2012 ISCAS https://doi.org/10.1109/ISCAS.2012.6271624 conf/iscas/2012 db/conf/iscas/iscas2012.html#YangLHLCCCHJLLLSWLH12 Geng-Cing Lin Shao-Cheng Wang Yi-Wei Lin Ming-Chien Tsai Ching-Te Chuang Shyh-Jye Jou Nan-Chun Lien Wei-Chiang Shih Kuen-Di Lee Jyun-Kai Chu An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. 2485-2488 2012 ISCAS https://doi.org/10.1109/ISCAS.2012.6271804 conf/iscas/2012 db/conf/iscas/iscas2012.html#LinWLTCJLSLC12 Yi-Wei Lin Hao-I Yang Geng-Cing Lin Chi-Shin Chang Ching-Te Chuang Wei Hwang Chia-Cheng Chen Willis Shih Huan-Shun Huang A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. 79-84 2012 ISLPED https://doi.org/10.1145/2333660.2333682 conf/islped/2012 db/conf/islped/islped2012.html#LinYLCCHCSH12 Hao-Yu Yang Chen-Wei Lin Hung-Hsin Chen Mango Chia-Tso Chao Ming-Hsien Tu Shyh-Jye Jou Ching-Te Chuang Testing strategies for a 9T sub-threshold SRAM. 1-10 2012 ITC https://doi.org/10.1109/TEST.2012.6401577 https://doi.ieeecomputersociety.org/10.1109/TEST.2012.6401577 conf/itc/2012 db/conf/itc/itc2012.html#YangLCCTJC12 Yung-Wei Lin Hao-I Yang Mao-Chih Hsia Yi-Wei Lin Chien-Hen Chen Ching-Te Chuang Wei Hwang Nan-Chun Lien Kuen-Di Lee Wei-Chiang Shih Ya-Ping Wu Wen-Ta Lee Chih-Chiang Hsu A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. 218-223 2012 SoCC https://doi.org/10.1109/SOCC.2012.6398351 conf/socc/2012 db/conf/socc/socc2012.html#LinYHLCCHLLSWLH12 Tzu-Ting Chiang Po-Tsang Huang Ching-Te Chuang Kuan-Neng Chen Jin-Chern Chiou Kuo-Hua Chen Chi-Tsung Chiu Ho-Ming Tong Wei Hwang On-chip self-calibrated process-temperature sensor for TSV 3D integration. 370-375 2012 SoCC https://doi.org/10.1109/SOCC.2012.6398338 conf/socc/2012 db/conf/socc/socc2012.html#ChiangHCCCCCTH12 Yi-Wei Lin Ming-Chien Tsai Hao-I Yang Geng-Cing Lin Shao-Cheng Wang Ching-Te Chuang Shyh-Jye Jou Wei Hwang Nan-Chun Lien Kuen-Di Lee Wei-Chiang Shih An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 1-4 2012 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2012.6212589 conf/vlsi-dat/2012 db/conf/vlsi-dat/vlsi-dat2012.html#LinTYLWCJHLLS12 Ming-Chien Tsai Yi-Wei Lin Hao-I Yang Ming-Hsien Tu Wei-Chiang Shih Nan-Chun Lien Kuen-Di Lee Shyh-Jye Jou Ching-Te Chuang Wei Hwang Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. 1-4 2012 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2012.6212587 conf/vlsi-dat/2012 db/conf/vlsi-dat/vlsi-dat2012.html#TsaiLYTSLLJCH12

Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. 335-342 2011 1 IEEE J. Emerg. Sel. Topics Circuits Syst. 3 https://doi.org/10.1109/JETCAS.2011.2163691 db/journals/esticas/esticas1.html#HuFSC11

Hao-I Yang Wei Hwang Ching-Te Chuang Impacts of gate-oxide breakdown on power-gated SRAM. 101-112 2011 42 Microelectron. J. 1 https://doi.org/10.1016/j.mejo.2010.08.020 db/journals/mj/mj42.html#YangHC11

Hao-I Yang Shyh-Chyi Yang Wei Hwang Ching-Te Chuang Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. 1239-1251 2011 58-I IEEE Trans. Circuits Syst. I Regul. Pap. 6 https://doi.org/10.1109/TCSI.2010.2096112 db/journals/tcas/tcasI58.html#YangYHC11

Saibal Mukhopadhyay Rahul M. Rao Jae-Joon Kim Ching-Te Chuang SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. 24-32 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2009.2029114 db/journals/tvlsi/tvlsi19.html#MukhopadhyayRKC11

Hao-I Yang Wei Hwang Ching-Te Chuang Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. 1192-1204 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2010.2049038 db/journals/tvlsi/tvlsi19.html#YangHC11

Vita Pi-Ho Hu Ming-Long Fan Pin Su Ching-Te Chuang Analysis of power-performance for ultra-thin-body GeOI logic circuits. 115-120 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016835&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#HuFSC11 Yi-Wei Chiu Jihi-Yu Lin Ming-Hsien Tu Shyh-Jye Jou Ching-Te Chuang 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. 169-174 2011 ISLPED http://portal.acm.org/citation.cfm?id=2016846&CFID=34981777&CFTOKEN=25607807 conf/islped/2011 db/conf/islped/islped2011.html#ChiuLTJC11 Hao-I Yang Shih-Chi Yang Mao-Chih Hsia Yung-Wei Lin Yi-Wei Lin Chien-Hen Chen Chi-Shin Chang Geng-Cing Lin Yin-Nien Chen Ching-Te Chuang Wei Hwang Shyh-Jye Jou Nan-Chun Lien Hung-Yu Li Kuen-Di Lee Wei-Chiang Shih Ya-Ping Wu Wen-Ta Lee Chih-Chiang Hsu A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. 197-200 2011 SoCC https://doi.org/10.1109/SOCC.2011.6085080 conf/socc/2011 db/conf/socc/socc2011.html#YangYHLLCCLCCHJLLLSWLH11

Ming-Hsien Tu Jihi-Yu Lin Ming-Chien Tsai Shyh-Jye Jou Ching-Te Chuang Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. 3039-3047 2010 57-I IEEE Trans. Circuits Syst. I Regul. Pap. 12 https://doi.org/10.1109/TCSI.2010.2071690 db/journals/tcas/tcasI57.html#TuLTJC10

Niladri Narayan Mojumder Saibal Mukhopadhyay Jae-Joon Kim Ching-Te Chuang Kaushik Roy 0001 Self-Repairing SRAM Using On-Chip Detection and Compensation. 75-84 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2008.2008808 db/journals/tvlsi/tvlsi18.html#MojumderMKCR10

Rajiv V. Joshi Saibal Mukhopadhyay Donald W. Plass Yuen H. Chan Ching-Te Chuang Yue Tan Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. 965-976 2009 44 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/JSSC.2009.2013768 db/journals/jssc/jssc44.html#JoshiMPCCT09

Aditya Bansal Rahul M. Rao Jae-Joon Kim Sufi Zafar James H. Stathis Ching-Te Chuang Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. 642-649 2009 49 Microelectron. Reliab. 6 https://doi.org/10.1016/j.microrel.2009.03.016 db/journals/mr/mr49.html#BansalRKZSC09

Aditya Bansal Rama N. Singh Rouwaida Kanj Saibal Mukhopadhyay Jin-Fuw Lee Emrah Acar Amith Singhee Keunwoo Kim Ching-Te Chuang Sani R. Nassif Fook-Luen Heng Koushik K. Das Yield estimation of SRAM circuits using "Virtual SRAM Fab". 631-636 2009 ICCAD https://doi.org/10.1145/1687399.1687516 https://ieeexplore.ieee.org/document/5361230/ conf/iccad/2009 db/conf/iccad/iccad2009.html#BansalSKMLASKCNHD09 Hao-I Yang Ching-Te Chuang Wei Hwang Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. 377-380 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5117764 conf/iscas/2009 db/conf/iscas/iscas2009.html#YangCH09 Amlan Ghosh Richard B. Brown Rahul M. Rao Ching-Te Chuang A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. 381-384 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5117765 conf/iscas/2009 db/conf/iscas/iscas2009.html#GhoshBRC09 Ching-Te Chuang Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits. 2305-2308 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5118260 conf/iscas/2009 db/conf/iscas/iscas2009.html#Chuang09 Vita Pi-Ho Hu Yu-Sheng Wu Ming-Long Fan Pin Su Ching-Te Chuang Design and analysis of ultra-thin-body SOI based subthreshold SRAM. 9-14 2009 ISLPED https://doi.org/10.1145/1594233.1594238 conf/islped/2009 db/conf/islped/islped2009.html#HuWFSC09 Jihi-Yu Lin Ming-Hsien Tu Ming-Chien Tsai Shyh-Jye Jou Ching-Te Chuang Asymmetrical Write-assist for single-ended SRAM operation. 101-104 2009 SoCC conf/socc/2009 db/conf/socc/socc2009.html#LinTTJC09 https://doi.org/10.1109/SOCCON.2009.5398086

Saibal Mukhopadhyay Keunwoo Kim Keith A. Jenkins Ching-Te Chuang Kaushik Roy 0001 An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. 1951-1963 2008 43 IEEE J. Solid State Circuits 9 https://doi.org/10.1109/JSSC.2008.2001896 db/journals/jssc/jssc43.html#MukhopadhyayKJC08

Koushik K. Das Ching-Te Chuang Richard B. Brown Reducing parasitic BJT effects in partially depleted SOI digital logic circuits. 275-285 2008 39 Microelectron. J. 2 https://doi.org/10.1016/j.mejo.2007.12.001 db/journals/mj/mj39.html#DasCB08

Jente B. Kuang Keunwoo Kim Ching-Te Chuang Hung C. Ngo Fadi H. Gebara Kevin J. Nowka Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. 1657-1665 2008 16 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2008.2001564 db/journals/tvlsi/tvlsi16.html#KuangKCNGN08

Aditya Bansal Rama N. Singh Saibal Mukhopadhyay Geng Han Fook-Luen Heng Ching-Te Chuang Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. 457-462 2008 ICCD https://doi.org/10.1109/ICCD.2008.4751901 https://doi.ieeecomputersociety.org/10.1109/ICCD.2008.4751901 conf/iccd/2008 db/conf/iccd/iccd2008.html#BansalSMHHC08 Saibal Mukhopadhyay Rahul M. Rao Jae-Joon Kim Ching-Te Chuang Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. 384-387 2008 ISCAS https://doi.org/10.1109/ISCAS.2008.4541435 conf/iscas/2008 db/conf/iscas/iscas2008.html#MukhopadhyayRKC08 Saibal Mukhopadhyay Rajiv V. Joshi Keunwoo Kim Ching-Te Chuang Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. 488-491 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479783 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.146 conf/isqed/2008 db/conf/isqed/isqed2008.html#MukhopadhyayJKC08 Amlan Ghosh Rahul M. Rao Ching-Te Chuang Richard B. Brown On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. 815-820 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479843 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.120 conf/isqed/2008 db/conf/isqed/isqed2008.html#GhoshRCB08 Aditya Bansal Jae-Joon Kim Keunwoo Kim Saibal Mukhopadhyay Ching-Te Chuang Kaushik Roy 0001 Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. 125-130 2008 VLSI Design https://doi.org/10.1109/VLSI.2008.50 https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.50 conf/vlsid/2008 db/conf/vlsid/vlsid2008.html#BansalKKMCR08 Amlan Ghosh Rahul M. Rao Jae-Joon Kim Ching-Te Chuang Richard B. Brown On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. 143-149 2008 VLSI Design https://doi.org/10.1109/VLSI.2008.67 https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.67 conf/vlsid/2008 db/conf/vlsid/vlsid2008.html#GhoshRKCB08 Niladri Narayan Mojumder Saibal Mukhopadhyay Jae-Joon Kim Ching-Te Chuang Kaushik Roy 0001 Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. 101-106 2008 VTS https://doi.org/10.1109/VTS.2008.26 https://doi.ieeecomputersociety.org/10.1109/VTS.2008.26 conf/vts/2008 db/conf/vts/vts2008.html#MojumderMKCR08

Saibal Mukhopadhyay Keunwoo Kim Jae-Joon Kim Shih-Hsien Lo Rajiv V. Joshi Ching-Te Chuang Kaushik Roy 0001 Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. 931-941 2007 38 Microelectron. J. 8-9 https://doi.org/10.1016/j.mejo.2006.03.010 db/journals/mj/mj38.html#MukhopadhyayKKLJCR07

Rajiv V. Joshi Rouwaida Kanj Keunwoo Kim Richard Q. Williams Ching-Te Chuang A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. 8-13 2007 ISLPED https://doi.org/10.1145/1283780.1283784 conf/islped/2007 db/conf/islped/islped2007.html#JoshiKKWC07 Saibal Mukhopadhyay Keunwoo Kim Ching-Te Chuang Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. 20-25 2007 ISLPED https://doi.org/10.1145/1283780.1283786 conf/islped/2007 db/conf/islped/islped2007.html#MukhopadhyayKC07 Jie Deng Keunwoo Kim Ching-Te Chuang H.-S. Philip Wong Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. 145-152 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.60 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.60 db/conf/isqed/isqed2007.html#DengKCW07 Saibal Mukhopadhyay Keunwoo Kim Keith A. Jenkins Ching-Te Chuang Kaushik Roy 0001 Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. 400-611 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373463 conf/isscc/2007 db/conf/isscc/isscc2007.html#MukhopadhyayKJCR07 Rajiv V. Joshi Keunwoo Kim Richard Q. Williams Edward J. Nowak Ching-Te Chuang A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. 665-672 2007 conf/vlsid/2007 VLSI Design https://doi.org/10.1109/VLSID.2007.182 https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.182 db/conf/vlsid/vlsid2007.html#JoshiKWNC07

Saibal Mukhopadhyay Keunwoo Kim Ching-Te Chuang Kaushik Roy 0001 Modeling and Analysis of Leakage Currents in Double-Gate Technologies. 2052-2061 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2006.873892 db/journals/tcad/tcad25.html#MukhopadhyayKCR06

Koushik K. Das Shih-Hsien Lo Ching-Te Chuang High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. 758-761 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.97 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.97 db/conf/vlsid/vlsid2006.html#DasLC06 Saibal Mukhopadhyay Keunwoo Kim Ching-Te Chuang Kaushik Roy 0001 Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. 8-13 2005 conf/islped/2005 ISLPED https://doi.org/10.1145/1077603.1077608 db/conf/islped/islped2005.html#MukhopadhyayKCR05 Saibal Mukhopadhyay Keunwoo Kim Jae-Joon Kim Shih-Hsien Lo Rajiv V. Joshi Ching-Te Chuang Kaushik Roy 0001 Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. 410-415 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.77 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.77 db/conf/isqed/isqed2005.html#MukhopadhyayKKLJCR05 Rajiv V. Joshi S. S. Kang N. Zamdmar Anda Mocuta Ching-Te Chuang J. A. Pascual-Gutiérrez Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. 697-702 2005 conf/vlsid/2005 VLSI Design https://doi.org/10.1109/ICVD.2005.82 https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.82 db/conf/vlsid/vlsid2005.html#JoshiKZMCP05

Jente B. Kuang Ching-Te Chuang Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits. 349-353 2004 51-II IEEE Trans. Circuits Syst. II Express Briefs 7 https://doi.org/10.1109/TCSII.2004.831428 https://www.wikidata.org/entity/Q113088978 db/journals/tcas/tcasII51.html#KuangC04

Rajiv V. Joshi Saibal Mukhopadhyay Donald W. Plass Yuen H. Chan Ching-Te Chuang Anirudh Devgan Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. 211-214 2004 ESSCIRC https://doi.org/10.1109/ESSCIR.2004.1356655 conf/esscirc/2004 db/conf/esscirc/esscirc2004.html#JoshiMPCCD04 Keunwoo Kim Koushik K. Das Rajiv V. Joshi Ching-Te Chuang Nanoscale CMOS circuit leakage power reduction by double-gate device. 102-107 2004 conf/islped/2004 ISLPED https://doi.org/10.1145/1013235.1013267 db/conf/islped/islped2004.html#KimDJC04 Rajiv V. Joshi K. Kroell Ching-Te Chuang A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. 832- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1261035 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261035 db/conf/vlsid/vlsid2004.html#JoshiKC04

Rosana Rodríguez James H. Stathis Barry P. Linder Rajiv V. Joshi Ching-Te Chuang Influence and model of gate oxide breakdown on CMOS inverters. 1439-1444 2003 43 Microelectron. Reliab. 9-11 https://doi.org/10.1016/S0026-2714(03)00247-6 db/journals/mr/mr43.html#RodriguezSLJC03

Rajiv V. Joshi Ching-Te Chuang Samuel K. H. Fung Fari Assaderaghi Melanie Sherony I. Yang Ghavam V. Shahidi PD/SOI SRAM performance in presence of gate-to-body tunneling current. 1106-1113 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2003.817552 db/journals/tvlsi/tvlsi11.html#JoshiCFASYS03

Koushik K. Das Rajiv V. Joshi Ching-Te Chuang Peter W. Cook Richard B. Brown New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. 309-312 2003 ESSCIRC https://doi.org/10.1109/ESSCIRC.2003.1257134 conf/esscirc/2003 db/conf/esscirc/esscirc2003.html#DasJCCB03 Kerry Bernstein Ching-Te Chuang Rajiv V. Joshi Ruchir Puri Design and CAD Challenges in sub-90nm CMOS Technologies. 129-137 2003 conf/iccad/2003 ICCAD https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257609 https://dl.acm.org/citation.cfm?id=1009880 db/conf/iccad/iccad2003.html#BernsteinCJP03 Koushik K. Das Rajiv V. Joshi Ching-Te Chuang Peter W. Cook Richard B. Brown New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. 168-171 2003 conf/islped/2003 ISLPED https://doi.org/10.1145/871506.871548 db/conf/islped/islped2003.html#DasJCCB03 Keunwoo Kim Rajiv V. Joshi Ching-Te Chuang Strained-si devices and circuits for low-power applications. 180-183 2003 conf/islped/2003 ISLPED https://doi.org/10.1145/871506.871551 db/conf/islped/islped2003.html#KimJC03 Ching-Te Chuang Rajiv V. Joshi Ruchir Puri Keunwoo Kim Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. 153-158 2003 conf/isqed/2003 ISQED https://doi.org/10.1109/ISQED.2003.1194724 https://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194724 db/conf/isqed/isqed2003.html#ChuangJPK03

Rosana Rodríguez James H. Stathis Barry P. Linder Steven P. Kowalczyk Ching-Te Chuang Rajiv V. Joshi Gregory A. Northrop Kerry Bernstein Azeez J. Bhavnagarwala Salvatore Lombardo Analysis of the effect of the gate oxide breakdown on SRAM stability. 1445-1448 2002 42 Microelectron. Reliab. 9-11 https://doi.org/10.1016/S0026-2714(02)00166-X db/journals/mr/mr42.html#RodriguezSLKCJNBBL02

Ruchir Puri Ching-Te Chuang Mark B. Ketchen Mario M. Pelella Michael G. Rosenfield On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits. 290-298 2001 36 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/4.902770 db/journals/jssc/jssc36.html#PuriCKPMR01

Jente B. Kuang David H. Allen Ching-Te Chuang Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology. 597-604 2001 36 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.913737 https://www.wikidata.org/entity/Q56952504 db/journals/jssc/jssc36.html#KuangAC01

Rajiv V. Joshi Wei Hwang Ching-Te Chuang SOI for asynchronous dynamic circuits. 37-42 2001 conf/glvlsi/2001 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/368122.368734 db/conf/glvlsi/glvlsi2001.html#JoshiHC01

Ruchir Puri Ching-Te Chuang Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits. 625-631 2000 35 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.839922 db/journals/jssc/jssc35.html#PuriC00

Rajiv V. Joshi Wei Hwang S. C. Wilson Ching-Te Chuang "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). 203-206 2000 conf/islped/2000 ISLPED https://doi.org/10.1145/344166.344586 db/conf/islped/islped2000.html#JoshiHWC00 Rajiv V. Joshi Wei Hwang S. C. Wilson Ghavam V. Shahidi Ching-Te Chuang A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. 44-49 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812583 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812583 db/conf/vlsid/vlsid2000.html#JoshiHWSC00 Ruchir Puri Ching-Te Chuang SOI Digital Circuits: Design Issues. 474-479 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812652 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812652 db/conf/vlsid/vlsid2000.html#PuriC00 Ching-Te Chuang Ruchir Puri SOI Digital CMOS VLSI - a Design Perspective. 709-714 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.310034 db/conf/dac/dac99.html#ChuangP99 Ruchir Puri Ching-Te Chuang Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. 223-228 1999 conf/islped/1999 ISLPED https://doi.org/10.1145/313817.313931 db/conf/islped/islped1999.html#PuriC99

Ching-Te Chuang Pong-Fei Lu Carl J. Anderson SOI for digital CMOS VLSI: design considerations and advances. 689-720 1998 86 Proc. IEEE 4 https://doi.org/10.1109/5.663545 db/journals/pieee/pieee86.html#ChuangLA98

Leon J. Sigal James D. Warnock Brian W. Curran Yuen H. Chan Peter J. Camporese Mark D. Mayo William V. Huott Daniel R. Knebel Ching-Te Chuang James P. Eckhardt Philip T. Wu Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. 489-504 1997 41 IBM J. Res. Dev. 4&5 https://doi.org/10.1147/rd.414.0489 db/journals/ibmrd/ibmrd41.html#SigalWCCCMHKCEW97

Pong-Fei Lu Ching-Te Chuang Jin Ji Lawrence F. Wagner Chang-Ming Hsieh Jente B. Kuang Louis Lu-Chen Hsu Mario M. Pelella Jr. Shao-Fu Sanford Chu Carl J. Anderson Floating-body effects in partially depleted SOI CMOS circuits. 1241-1253 1997 32 IEEE J. Solid State Circuits 8 https://doi.org/10.1109/4.604080 db/journals/jssc/jssc32.html#LuCJWHKHPCA97

Charles F. Webb Carl J. Anderson Leon J. Sigal Kenneth L. Shepard John S. Liptay James D. Warnock Brian W. Curran Barry Krumm Mark D. Mayo Peter J. Camporese Eric M. Schwarz Mark S. Farrell Phillip J. Restle Robert M. Averill III Timothy J. Slegel William V. Huott Yuen H. Chan Bruce Wile Thao N. Nguyen Philip G. Emma Daniel K. Beece Ching-Te Chuang Cyril Price A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. 1676-1682 1997 32 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.641687 db/journals/jssc/jssc32.html#WebbASSLWCKMCSF97

Pong-Fei Lu Jin Ji Ching-Te Chuang Lawrence F. Wagner Chang-Ming Hsieh Jente Benedict Kuang L. Hsu Mario M. Pelella Jr. Shao-Fu Sanford Chu Carl J. Anderson Floating body effects in partially-depleted SOI CMOS circuits. 139-144 1996 conf/islped/1996 ISLPED https://doi.org/10.1109/LPE.1996.547496 https://dl.acm.org/citation.cfm?id=252590 db/conf/islped/islped1996.html#LuJCWHKHPCA96

Ching-Te Chuang B. Wu C. J. Anderson High-speed low-power cross-coupled active-pull-down ECL circuit. 701-705 1995 June 30 IEEE J. Solid State Circuits 6 https://doi.org/10.1109/4.387076 db/journals/jssc/jssc30.html#ChuangWA95

Ching-Te Chuang Kenneth Chin High-speed low-power direct-coupled complementary push-pull ECL circuit. 836-839 1994 July 29 IEEE J. Solid State Circuits 7 https://doi.org/10.1109/4.303723 db/journals/jssc/jssc29.html#ChuangC94

Hsueh Y. Hsieh Kenneth Chin Ching-Te Chuang Power partition and emitter size optimization for bipolar ECL circuit. 548-552 1993 May 28 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.229401 db/journals/jssc/jssc28.html#HsiehCC93 streams/journals/jssc

B. S. Wu Ching-Te Chuang Kenneth Chin Non-quasi-static effects in advanced high-speed bipolar circuits. 613-617 1993 May 28 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.229392 db/journals/jssc/jssc28.html#WuCC93 streams/journals/jssc

Ching-Te Chuang Kenneth Chin Pong-Fei Lu Hyun J. Shin High-speed low-power Darlington ECL circuit. 1374-1376 1993 December 28 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/4.262014 db/journals/jssc/jssc28.html#ChuangCLS93 streams/journals/jssc

Ching-Te Chuang Kenneth Chin Johannes M. C. Stork Gary L. Patton Emmanuel F. Crabbé James H. Comfort On the leverage of high-f<sub>T</sub> transistors for advanced high-speed bipolar circuits. 225-228 1992 February 27 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/4.127348 db/journals/jssc/jssc27.html#ChuangCSPCC92 streams/journals/jssc

Ching-Te Chuang Denny D. Tang High-speed low-power AC-coupled complementary push-pull ECL circuit. 660-663 1992 April 27 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.126558 db/journals/jssc/jssc27.html#ChuangT92 streams/journals/jssc

Ching-Te Chuang Kenneth Chin Hyun J. Shin Pong-Fei Lu High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. 1207-1210 1992 August 27 IEEE J. Solid State Circuits 8 https://doi.org/10.1109/4.148331 db/journals/jssc/jssc27.html#ChuangCSL92 streams/journals/jssc

Kenneth Chin Ching-Te Chuang James D. Warnock 12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit. 1648-1650 1992 November 27 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.165347 db/journals/jssc/jssc27.html#ChinCW92 streams/journals/jssc

Ching-Te Chuang NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit. 661-665 1991 April 26 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.75070 db/journals/jssc/jssc26.html#Chuang91 streams/journals/jssc

Hyun J. Shin Pong-Fei Lu Ching-Te Chuang A high-speed low-power JFET pull-down ECL circuit. 679-683 1991 April 26 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.75075 db/journals/jssc/jssc26.html#ShinLC91 streams/journals/jssc

Ching-Te Chuang Kenneth Chin High-speed low-power charge-buffered active-pull-down ECI circuit. 812-815 1991 May 26 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.78253 db/journals/jssc/jssc26.html#ChuangC91 streams/journals/jssc

Kai-Yap Toh Ching-Te Chuang Tze-Chiang Chen James D. Warnock A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage. 1301-1306 1989 October 24 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.1989.572601 db/journals/jssc/jssc24.html#TohCCW89 streams/journals/jssc

Denny D. Tang Ching-Te Chuang A circuit concept for reducing soft error in high-speed memory cells. 201-203 1988 February 23 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/4.279 db/journals/jssc/jssc23.html#TangC88 streams/journals/jssc

Emrah Acar David H. Allen C. J. Anderson Carl J. Anderson Fari Assaderaghi Robert M. Averill III Aditya Bansal Daniel K. Beece Kerry Bernstein Azeez BhavnagarwalaAzeez J. Bhavnagarwala Richard B. Brown Peter J. Camporese Yuen H. Chan Yun-Sheng Chan Chi-Shin Chang Chia-Ning Chang Chih-Wei Chang Fung-Kai Chang Hsiao-Chun Chang Ming-Hung Chang Nien-Shang Chang Zhi-Hao Chang Mango Chia-Tso Chao Chi-Shi Chen Chia-Cheng Chen Chien-Hen Chen Chien-Ju Chen Hung-Hsin Chen Hung-Lieh Chen Kuan-Neng Chen Kuo-Hua Chen Ming Chen Tze-Chiang Chen Yin-Nien Chen Yu-Hsian Chen Cheng-Yo Cheng Chuan-An Cheng Ming-Hsiang Cheng Tzu-Ting Chiang Yu-San Chien Kenneth Chin Jin-Chern Chiou Chi-Tsung Chiu Tzai-Wen Chiu Yi-Wei Chiu Lei-Chun Chou Jyun-Kai Chu Li-Wei Chu Shao-Fu Sanford Chu Yuan-Hua Chu Chao-Kuei Chung James H. Comfort Peter W. Cook Emmanuel F. Crabbé Brian W. Curran Koushik K. Das Jie Deng Anirudh Devgan Jeng-Ren Duann James P. Eckhardt Philip G. Emma Ming-Long Fan Mark S. Farrell Samuel K. H. Fung Fadi H. Gebara Amlan Ghosh Geng Han Fook-Luen Heng Mao-Chih Hsia Chang-Ming Hsieh Chien-Yu Hsieh Hsueh Y. Hsieh Chih-Chiang Hsu L. Hsu Louis Lu-Chen Hsu Angelo Hu Vita Pi-Ho Hu Yong-Jyun Hu Yu-Chen Hu Yu-Hao Hu Chun-Ying Huang Chung-Ping Huang Huan-Shun Huang Jason Huang Po-Tsang Huang Teng-Chieh Huang Yan-Pin Huang Yan-Yu Huang Yu-Chieh Huang William V. Huott Wei Hwang Keith A. Jenkins Jin Ji Michael Jia Rajiv V. Joshi Shyh-Jye Jou Paul Kan Paul-Sen Kan S. S. Kang Rouwaida Kanj Yung-Shin Kao Mark B. Ketchen Jae-Joon Kim Keunwoo Kim Daniel R. Knebel Steven P. Kowalczyk K. Kroell Barry Krumm Jente B. KuangJente Benedict Kuang Yi-Ping Kuo Shu-Lin Lai Jin-Fuw Lee Kuen-Di Lee Shih-Wei Lee Wen-Ta Lee Yen-Chi Lee Hung-Yu Li Kuang-Yu Li Yu-Jie Liang Wei-Nan Liao Nan-Chun Lien Chen-Wei Lin Chun-Pin Lin Geng-Cing Lin Hon-Jarn Lin Jihi-Yu Lin Shang-Yuan Lin Teu-Hua Lin Yen-Han Lin Yi-Wei Lin Yu-Rou Lin Yueh-Lung Lin Yuh-Jiun Lin Yung-Wei Lin Barry P. Linder John S. Liptay Shih-Hsien Lo Salvatore Lombardo Chien-Yu Lu Ming-Wei Lu Pong-Fei Lu Sheng-Chi Lung Kimi Lv Mark D. Mayo Anda Mocuta Niladri Narayan Mojumder Saibal Mukhopadhyay Sani R. Nassif Hung C. Ngo Thao N. Nguyen Gregory A. Northrop Edward J. Nowak Kevin J. Nowka Chia-Hao Pao J. A. Pascual-Gutiérrez Gary L. Patton Mario M. Pelella Mario M. Pelella Jr. Wei-Sheng Peng Donald W. Plass Cyril Price Ruchir Puri Rahul M. Rao Phillip J. Restle Rosana Rodríguez Michael G. Rosenfield Kaushik Roy 0001 Eric M. Schwarz Ghavam V. Shahidi Wen-Wei Shen Ting-Wei Sheng Kenneth L. Shepard Melanie Sherony Wei-Chiang Shih Willis Shih Hyun J. Shin Ming-Shaw Shy Leon J. Sigal Rama N. Singh Amith Singhee Timothy J. Slegel James H. Stathis Johannes M. C. Stork Pin Su Yue Tan Denny D. Tang Kai-Yap Toh Ho-Ming Tong Jen-Huan Tsai Ming-Chien Tsai Ming-Fu Tsai Huan-Jan Tseng Ming-Hsien Tu Ruoh-Ning Tzeng Lawrence F. Wagner Chen-Chao Wang Dao-Ping Wang Jian-Hao Wang Meng-Hsueh Wang Shao-Cheng Wang Tang-Hsuan Wang Tang-Shuan Wang Wei-Chang Wang James D. Warnock Charles F. Webb Bruce Wile Richard Q. Williams S. C. Wilson H.-S. Philip Wong B. Wu B. S. Wu Chung-Hsi Wu Chung-Shiang Wu Pei-Chen Wu Philip T. Wu Shang-Lin Wu Tse-Ching Wu Wen-Rong Wu Ya-Ping Wu Yi-Chun Wu Yu-Sheng Wu Chih-Chao Yang Hao-I Yang Hao-Yu Yang I. Yang Shaoyu YangShao-Yu Yang Shih-Chi Yang Shyh-Chyi Yang Yan-Huei You Chang-Hung Yu Sufi Zafar Olesya Zakoretska N. Zamdmar Bright Zhang Jun-Kai Zhao