Theoretical complexity analysis of many-cores on a single chip.

Ran Ginosar

Ran Ginosar Theoretical complexity analysis of many-cores on a single chip. 2025 February abs/2502.00153 CoRR https://doi.org/10.48550/arXiv.2502.00153 db/journals/corr/corr2502.html#abs-2502-00153 streams/journals/corr

Leonid Yavits Roman Kaplan Ran Ginosar GIRAF: General Purpose In-Storage Resistive Associative Framework. 276-287 2022 33 IEEE Trans. Parallel Distributed Syst. 2 https://doi.org/10.1109/TPDS.2021.3065448 db/journals/tpds/tpds33.html#YavitsKG22

Leonid Azriel Julian Speith Nils Albartus Ran Ginosar Avi Mendelson Christof Paar A survey of algorithmic methods in IC reverse engineering. 299-315 2021 11 J. Cryptogr. Eng. 3 https://doi.org/10.1007/s13389-021-00268-5 https://www.wikidata.org/entity/Q114848890 db/journals/jce/jce11.html#AzrielSAGMP21

Leonid Azriel Julian Speith Nils Albartus Ran Ginosar Avi Mendelson Christof Paar A survey of algorithmic methods in IC reverse engineering. 1278 2021 2021 IACR Cryptol. ePrint Arch. https://eprint.iacr.org/2021/1278 db/journals/iacr/iacr2021.html#AzrielSAGMP21

Leonid Yavits Lois Orosa 0001 Suyash Mahar João Dinis Ferreira Mattan Erez Ran Ginosar Onur Mutlu WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. 187-196 2020 ICCD https://doi.org/10.1109/ICCD50377.2020.00044 conf/iccd/2020 db/conf/iccd/iccd2020.html#YavitsOMFEGM20 Roman Kaplan Leonid Yavits Ran Ginosar BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. 36-48 2020 SYSTOR https://doi.org/10.1145/3383669.3398279 conf/systor/2020 db/conf/systor/systor2020.html#KaplanYG20

Leonid Yavits Lois Orosa 0001 Suyash Mahar João Dinis Ferreira Mattan Erez Ran Ginosar Onur Mutlu WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. 2020 abs/2010.02825 CoRR https://arxiv.org/abs/2010.02825 db/journals/corr/corr2010.html#abs-2010-02825

Roman Kaplan Leonid Yavits Ran Ginosar RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. 44-54 2019 39 IEEE Micro 4 https://doi.org/10.1109/MM.2018.2890253 https://www.wikidata.org/entity/Q128690886 db/journals/micro/micro39.html#KaplanYG19

Misbah Ramadan Nicolás Wainstein Ran Ginosar Shahar Kvatinsky Adaptive programming in multi-level cell ReRAM. 169-180 2019 90 Microelectron. J. https://doi.org/10.1016/j.mejo.2019.06.004 db/journals/mj/mj90.html#RamadanWGK19

Roman Kaplan Leonid Yavits Ran Ginosar POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. 459-460 2019 PACT https://doi.org/10.1109/PACT.2019.00044 conf/IEEEpact/2019 db/conf/IEEEpact/pact2019.html#KaplanYG19 Leonid Yavits Roman Kaplan Ran Ginosar POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. 477-478 2019 PACT https://doi.org/10.1109/PACT.2019.00053 conf/IEEEpact/2019 db/conf/IEEEpact/pact2019.html#YavitsKG19 Leonid Azriel Ran Ginosar Avi Mendelson SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. 65-74 2019 ASHES@CCS https://doi.org/10.1145/3338508.3359575 conf/ccs/2019ashes db/conf/ccs/ashes2019.html#AzrielGM19

Leonid Yavits Roman Kaplan Ran Ginosar AIDA: Associative DNN Inference Accelerator. 2019 abs/1901.04976 CoRR http://arxiv.org/abs/1901.04976 db/journals/corr/corr1901.html#abs-1901-04976

Roman Kaplan Leonid Yavits Ran Ginosar BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. 2019 abs/1901.05959 CoRR http://arxiv.org/abs/1901.05959 db/journals/corr/corr1901.html#abs-1901-05959

Leonid Yavits Ran Ginosar Accelerator for Sparse Machine Learning. 21-24 2018 17 IEEE Comput. Archit. Lett. 1 https://doi.org/10.1109/LCA.2017.2714667 http://doi.ieeecomputersociety.org/10.1109/LCA.2017.2714667 db/journals/cal/cal17.html#YavitsG18

Leonid Yavits Roman Kaplan Ran Ginosar Enabling Full Associativity with Memristive Address Decoder. 32-40 2018 38 IEEE Micro 5 https://doi.org/10.1109/MM.2018.053631139 http://doi.ieeecomputersociety.org/10.1109/MM.2018.053631139 db/journals/micro/micro38.html#YavitsKG18

Leonid Yavits Roman Kaplan Ran Ginosar PRINS: Resistive CAM Processing in Storage. 2018 abs/1805.09612 CoRR http://arxiv.org/abs/1805.09612 db/journals/corr/corr1805.html#abs-1805-09612

Roman Kaplan Leonid Yavits Ran Ginosar RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. 2018 abs/1809.01127 CoRR http://arxiv.org/abs/1809.01127 db/journals/corr/corr1809.html#abs-1809-01127

Leonid Yavits Uri C. Weiser Ran Ginosar Resistive Address Decoder. 141-144 2017 16 IEEE Comput. Archit. Lett. 2 https://doi.org/10.1109/LCA.2017.2670539 http://doi.ieeecomputersociety.org/10.1109/LCA.2017.2670539 db/journals/cal/cal16.html#YavitsWG17

Y. Zhang Rostislav (Reuven) Dobkin Aharon Unikovski Danniel Nahmanny Goel Samuel Michael Moyal Ran Ginosar A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. 190-197 2017 59 Integr. https://doi.org/10.1016/j.vlsi.2017.06.007 db/journals/integration/integration59.html#ZhangDUNSMG17

Roman Kaplan Leonid Yavits Ran Ginosar Uri C. Weiser A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. 20-28 2017 37 IEEE Micro 4 https://doi.org/10.1109/MM.2017.3211121 http://doi.ieeecomputersociety.org/10.1109/MM.2017.3211121 db/journals/micro/micro37.html#KaplanYGW17

Roman Kaplan Leonid Yavits Ran Ginosar From Processing-in-Memory to Processing-in-Storage. 99-116 2017 4 Supercomput. Front. Innov. 3 https://doi.org/10.14529/jsfi170307 db/journals/superfri/superfri4.html#KaplanYG17

Leonid Azriel Ran Ginosar Shay Gueron Avi Mendelson Using Scan Side Channel to Detect IP Theft. 3268-3280 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2017.2715188 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2715188 db/journals/tvlsi/tvlsi25.html#AzrielGGM17

Leonid Azriel Ran Ginosar Avi Mendelson Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering. 233-238 2017 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3060403.3060464 conf/glvlsi/2017 db/conf/glvlsi/glvlsi2017.html#AzrielGM17

Roman Kaplan Leonid Yavits Ran Ginosar Uri C. Weiser A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. 2017 abs/1701.04723 CoRR http://arxiv.org/abs/1701.04723 db/journals/corr/corr1701.html#KaplanYGW17

Leonid Yavits Amir Morad Uri C. Weiser Ran Ginosar MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. 2017 abs/1705.06923 CoRR http://arxiv.org/abs/1705.06923 db/journals/corr/corr1705.html#YavitsMWG17

Leonid Yavits Amir Morad Ran Ginosar The Effect of Temperature on Amdahl Law in 3D Multicore Era. 2017 abs/1705.07280 CoRR http://arxiv.org/abs/1705.07280 db/journals/corr/corr1705.html#YavitsMG17

Leonid Yavits Amir Morad Ran Ginosar Cache Hierarchy Optimization. 2017 abs/1705.07281 CoRR http://arxiv.org/abs/1705.07281 db/journals/corr/corr1705.html#YavitsMG17a

Leonid Yavits Amir Morad Ran Ginosar Sparse Matrix Multiplication On An Associative Processor. 2017 abs/1705.07282 CoRR http://arxiv.org/abs/1705.07282 db/journals/corr/corr1705.html#YavitsMG17b

Leonid Yavits Ran Ginosar Sparse Matrix Multiplication on CAM Based Accelerator. 2017 abs/1705.09937 CoRR http://arxiv.org/abs/1705.09937 db/journals/corr/corr1705.html#YavitsG17

Efraim Rotem Uri C. Weiser Avi Mendelson Ran Ginosar Eliezer Weissmann Yoni Aizik H-EARtH: Heterogeneous Multicore Platform Energy Management. 47-55 2016 49 Computer 10 https://doi.org/10.1109/MC.2016.309 http://doi.ieeecomputersociety.org/10.1109/MC.2016.309 db/journals/computer/computer49.html#RotemWMGWA16

Amir Morad Leonid Yavits Shahar Kvatinsky Ran Ginosar Resistive GP-SIMD Processing-In-Memory. 57:1-57:22 2016 12 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2845084 db/journals/taco/taco12.html#MoradYKG16

Leonid Yavits Amir Morad Ran Ginosar The Effect of Temperature on Amdahl Law in 3D Multicore Era. 2010-2013 2016 65 IEEE Trans. Computers 6 https://doi.org/10.1109/TC.2015.2458865 http://doi.ieeecomputersociety.org/10.1109/TC.2015.2458865 db/journals/tc/tc65.html#YavitsMG16

Leonid Azriel Ran Ginosar Shay Gueron Avi Mendelson Using Scan Side Channel for Detecting IP Theft. 1:1-1:8 2016 HASP@ISCA https://doi.org/10.1145/2948618.2948619 conf/isca/2016hasp db/conf/isca/hasp2016.html#AzrielGGM16 Roman Kaplan Leonid Yavits Amir Morad Ran Ginosar Deduplication in resistive content addressable memory based solid state drive. 100-106 2016 PATMOS https://doi.org/10.1109/PATMOS.2016.7833432 conf/patmos/2016 db/conf/patmos/patmos2016.html#KaplanYMG16

Leonid Yavits Amir Morad Ran Ginosar Uri C. Weiser Convex Optimization of Real Time SoC. 2016 abs/1601.07815 CoRR http://arxiv.org/abs/1601.07815 db/journals/corr/corr1601.html#YavitsMGW16

Leonid Yavits Amir Morad Ran Ginosar Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. 2016 abs/1602.01329 CoRR http://arxiv.org/abs/1602.01329 db/journals/corr/corr1602.html#YavitsMG16

Leonid Yavits Shahar Kvatinsky Amir Morad Ran Ginosar Resistive Associative Processor. 148-151 2015 14 IEEE Comput. Archit. Lett. 2 https://doi.org/10.1109/LCA.2014.2374597 http://doi.ieeecomputersociety.org/10.1109/LCA.2014.2374597 db/journals/cal/cal14.html#YavitsKMG15

Efraim Rotem Ran Ginosar Avi Mendelson Uri C. Weiser Power and thermal constraints of modern system-on-a-chip computer. 1225-1229 2015 46 Microelectron. J. 12 https://doi.org/10.1016/j.mejo.2015.09.002 db/journals/mj/mj46.html#RotemGMW15

Leonid Yavits Amir Morad Ran Ginosar Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. 368-381 2015 64 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2013.220 http://doi.ieeecomputersociety.org/10.1109/TC.2013.220 db/journals/tc/tc64.html#YavitsMG15

Marco Cannizzaro Salomon Beer Jordi Cortadella Ran Ginosar Luciano Lavagno SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. 2238-2247 2015 62-I IEEE Trans. Circuits Syst. I Regul. Pap. 9 https://doi.org/10.1109/TCSI.2014.2365878 https://www.wikidata.org/entity/Q56891786 db/journals/tcas/tcasI62.html#CannizzaroBCGL15

Leonid Yavits Amir Morad Ran Ginosar Sparse Matrix Multiplication On An Associative Processor. 3175-3183 2015 26 IEEE Trans. Parallel Distributed Syst. 11 https://doi.org/10.1109/TPDS.2014.2370055 http://doi.ieeecomputersociety.org/10.1109/TPDS.2014.2370055 db/journals/tpds/tpds26.html#YavitsMG15

Salomon Beer Ran Ginosar Eleven Ways to Boost Your Synchronizer. 1040-1049 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2014.2331331 db/journals/tvlsi/tvlsi23.html#BeerG15

Salomon Beer Ran Ginosar A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance. 2461-2472 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2014.2365255 db/journals/tvlsi/tvlsi23.html#BeerG15a

Salomon Beer Jerome Cox Ran Ginosar Tom Chaney David M. Zar Variability in Multistage Synchronizers. 2957-2969 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2014.2387391 db/journals/tvlsi/tvlsi23.html#BeerCGCZ15

Ron Diamant Ran Ginosar Christos P. Sotiriou Asynchronous sub-threshold ultra-low power processor. 89-96 2015 PATMOS https://doi.org/10.1109/PATMOS.2015.7347592 conf/patmos/2015 db/conf/patmos/patmos2015.html#DiamantGS15

Efraim Rotem Ran Ginosar Uri C. Weiser Avi Mendelson Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. 25-28 2014 13 IEEE Comput. Archit. Lett. 1 https://doi.org/10.1109/L-CA.2012.32 http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.32 db/journals/cal/cal13.html#RotemGWM14

Amir Morad Tomer Y. Morad Leonid Yavits Ran Ginosar Uri C. Weiser Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. 37-40 2014 13 IEEE Comput. Archit. Lett. 1 https://doi.org/10.1109/L-CA.2012.34 http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.34 db/journals/cal/cal13.html#MoradMYGW14

Leonid Yavits Amir Morad Ran Ginosar Cache Hierarchy Optimization. 69-72 2014 13 IEEE Comput. Archit. Lett. 2 https://doi.org/10.1109/L-CA.2013.18 http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.18 db/journals/cal/cal13.html#YavitsMG14

Dmitry Verbitsky Rostislav (Reuven) Dobkin Ran Ginosar Salomon Beer StarSync: An extendable standard-cell mesochronous synchronizer. 250-260 2014 47 Integr. 2 https://doi.org/10.1016/j.vlsi.2013.09.003 db/journals/integration/integration47.html#VerbitskyDGB14

Leonid Yavits Amir Morad Ran Ginosar The effect of communication and synchronization on Amdahl's law in multicore systems. 1-16 2014 40 Parallel Comput. 1 https://doi.org/10.1016/j.parco.2013.11.001 db/journals/pc/pc40.html#YavitsMG14

Jawad Haj-Yihia Yosi Ben-Asher Efraim Rotem Ahmad Yasin Ran Ginosar Compiler-Directed Power Management for Superscalars. 48:1-48:21 2014 11 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2685393 https://www.wikidata.org/entity/Q121434968 db/journals/taco/taco11.html#Haj-YihiaBRYG14

Amir Morad Leonid Yavits Ran Ginosar GP-SIMD Processing-in-Memory. 53:1-53:26 2014 11 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2686875 db/journals/taco/taco11.html#MoradYG14

Ran Ginosar Karam S. Chatha Guest Editors' Introduction - Special Issue on Network-on-Chip. 527-528 2014 63 IEEE Trans. Computers 3 https://doi.org/10.1109/TC.2014.6 http://doi.ieeecomputersociety.org/10.1109/TC.2014.6 db/journals/tc/tc63.html#GinosarC14

Salomon Beer Marco Cannizzaro Jordi Cortadella Ran Ginosar Luciano Lavagno Metastability in Better-Than-Worst-Case Designs. 101-102 2014 ASYNC https://doi.org/10.1109/ASYNC.2014.21 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2014.21 https://www.wikidata.org/entity/Q56891806 conf/async/2014 db/conf/async/async2014.html#BeerCCGL14 Itai Avron Ran Ginosar Hardware Scheduler Performance on the Plural Many-Core Architecture. 48-51 2014 MES@ISCA https://doi.org/10.1145/2768177.2768184 conf/isca/2015mes db/conf/isca/mes2015.html#AvronG14 Amir Morad Leonid Yavits Ran Ginosar Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. 1-8 2014 PATMOS https://doi.org/10.1109/PATMOS.2014.6951895 conf/patmos/2014 db/conf/patmos/patmos2014.html#MoradYG14 Amir Morad Leonid Yavits Ran Ginosar Convex optimization of resource allocation in asymmetric and heterogeneous SoC. 1-8 2014 PATMOS https://doi.org/10.1109/PATMOS.2014.6951864 conf/patmos/2014 db/conf/patmos/patmos2014.html#MoradYG14a Efraim Rotem Uri C. Weiser Avi Mendelson Ahmad Yasin Ran Ginosar Energy management of highly dynamic server workloads in an heterogeneous data center. 1-5 2014 PATMOS https://doi.org/10.1109/PATMOS.2014.6951868 conf/patmos/2014 db/conf/patmos/patmos2014.html#RotemWMYG14

Ameer Abdelhadi Ran Ginosar Avinoam Kolodny Eby G. Friedman Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. 382-391 2013 46 Integr. 4 https://doi.org/10.1016/j.vlsi.2012.12.001 db/journals/integration/integration46.html#AbdelhadiGKF13

Leonid Yavits Amir Morad Ran Ginosar 3D cache hierarchy optimization. 1-5 2013 3DIC https://doi.org/10.1109/3DIC.2013.6702346 conf/3dic/2013 db/conf/3dic/3dic2013.html#YavitsMG13 Salomon Beer Ran Ginosar Rostislav (Reuven) Dobkin Yoav Weizman MTBF Estimation in Coherent Clock Domains. 166-173 2013 ASYNC https://doi.org/10.1109/ASYNC.2013.19 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2013.19 conf/async/2013 db/conf/async/async2013.html#BeerGDW13 Salomon Beer Ran Ginosar Jerome Cox Tom Chaney David M. Zar Metastability challenges for 65nm and beyond: simulation and measurements. 1297-1302 2013 DATE https://doi.org/10.7873/DATE.2013.268 http://dl.acm.org/citation.cfm?id=2485599 conf/date/2013 db/conf/date/date2013.html#BeerGCCZ13 Eyal-Itzhak Nave Ran Ginosar PBD: packet buffer DVFs. 319-320 2013 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/2483028.2483121 conf/glvlsi/2013 db/conf/glvlsi/glvlsi2013.html#NaveG13

Leonid Yavits Amir Morad Ran Ginosar The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. 2013 CoRR http://arxiv.org/abs/1306.3302 abs/1306.3302 db/journals/corr/corr1306.html#YavitsMG13a

Leonid Yavits Amir Morad Ran Ginosar Thermal analysis of 3D associative processor. 2013 CoRR http://arxiv.org/abs/1307.3853 abs/1307.3853 db/journals/corr/corr1307.html#YavitsMG13b

Leonid Yavits Amir Morad Ran Ginosar 3D Cache Hierarchy Optimization. 2013 CoRR http://arxiv.org/abs/1311.1667 abs/1311.1667 db/journals/corr/corr1311.html#YavitsMG13c

Itai Avron Ran Ginosar Performance of a Hardware Scheduler for Many-core Architecture. 151-160 2012 HPCC-ICESS https://doi.org/10.1109/HPCC.2012.29 https://doi.ieeecomputersociety.org/10.1109/HPCC.2012.29 conf/hpcc/2012 db/conf/hpcc/hpcc2012.html#AvronG12 Inna Vaisband Eby G. Friedman Ran Ginosar Avinoam Kolodny Energy metrics for power efficient crosslink and mesh topologies. 1656-1659 2012 ISCAS https://doi.org/10.1109/ISCAS.2012.6271575 conf/iscas/2012 db/conf/iscas/iscas2012.html#VaisbandFGK12 Salomon Beer Ran Ginosar An Extended Metastability Simulation Method for Synchronizer Characterization. 42-51 2012 PATMOS https://doi.org/10.1007/978-3-642-36157-9_5 conf/patmos/2012 db/conf/patmos/patmos2012.html#BeerG12 Eyal-Itzhak Nave Ran Ginosar TCP Window Based DVFS for Low Power Network Controller SoC. 83-92 2012 PATMOS https://doi.org/10.1007/978-3-642-36157-9_9 conf/patmos/2012 db/conf/patmos/patmos2012.html#NaveG12

Ran Ginosar Metastability and Synchronizers: A Tutorial. 23-35 2011 28 IEEE Des. Test Comput. 5 https://doi.org/10.1109/MDT.2011.113 http://doi.ieeecomputersociety.org/10.1109/MDT.2011.113 db/journals/dt/dt28.html#Ginosar11

Dmitri Vainbrand Ran Ginosar Scalable network-on-chip architecture for configurable neural networks. 152-166 2011 35 Microprocess. Microsystems 2 https://doi.org/10.1016/j.micpro.2010.08.005 db/journals/mam/mam35.html#VainbrandG11

Salomon Beer Ran Ginosar Michael Priel Rostislav (Reuven) Dobkin Avinoam Kolodny An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. 2593-2596 2011 ISCAS https://doi.org/10.1109/ISCAS.2011.5938135 conf/iscas/2011 db/conf/iscas/iscas2011.html#BeerGPDK11 Radu Marculescu Michael Kishinevsky Ran Ginosar Karam S. Chatha NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011 ACM/IEEE Computer Society NOCS 2011 978-1-4503-0720-8 https://doi.org/10.1145/1999946 https://ieeexplore.ieee.org/xpl/conhome/5936926/proceeding db/conf/nocs/nocs2011.html

Arkadiy Morgenshtein Eby G. Friedman Ran Ginosar Avinoam Kolodny Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. 689-696 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2009.2014239 db/journals/tvlsi/tvlsi18.html#MorgenshteinFGK10

Rostislav (Reuven) Dobkin Michael Moyal Avinoam Kolodny Ran Ginosar Asynchronous Current Mode Serial Communication. 1107-1117 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2009.2020859 db/journals/tvlsi/tvlsi18.html#DobkinMKG10

Arkadiy Morgenshtein Eby G. Friedman Ran Ginosar Avinoam Kolodny Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. 1262 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2010.2052421 db/journals/tvlsi/tvlsi18.html#MorgenshteinFGK10a

Salomon Beer Ran Ginosar Michael Priel Rostislav (Reuven) Dobkin Avinoam Kolodny The Devolution of Synchronizers. 94-103 2010 ASYNC https://doi.org/10.1109/ASYNC.2010.22 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2010.22 conf/async/2010 db/conf/async/async2010.html#BeerGPDK10 Ameer Abdelhadi Ran Ginosar Avinoam Kolodny Eby G. Friedman Timing-driven variation-aware nonuniform clock mesh synthesis. 15-20 2010 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1785481.1785487 conf/glvlsi/2010 db/conf/glvlsi/glvlsi2010.html#AbdelhadiGKF10 Dmitri Vainbrand Ran Ginosar Network-on-Chip Architectures for Neural Networks. 135-144 2010 NOCS https://doi.org/10.1109/NOCS.2010.23 https://doi.ieeecomputersociety.org/10.1109/NOCS.2010.23 conf/nocs/2010 db/conf/nocs/nocs2010.html#VainbrandG10 Amit Berman Ran Ginosar Idit Keidar Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. 37-42 2010 VLSI-SoC https://doi.org/10.1109/VLSISOC.2010.5642624 conf/vlsi/2010soc db/conf/vlsi/vlsisoc2010.html#BermanGK10

Rostislav (Reuven) Dobkin Ran Ginosar Avinoam Kolodny QNoC asynchronous router. 103-115 2009 42 Integr. 2 https://doi.org/10.1016/j.vlsi.2008.03.001 db/journals/integration/integration42.html#DobkinGK09

Rostislav (Reuven) Dobkin Ran Ginosar Two-phase synchronization with sub-cycle latency. 367-375 2009 42 Integr. 3 https://doi.org/10.1016/j.vlsi.2008.11.006 db/journals/integration/integration42.html#DobkinG09

Inna Vaisband Ran Ginosar Avinoam Kolodny Eby G. Friedman Power efficient tree-based crosslinks for skew reduction. 285-290 2009 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1531542.1531609 conf/glvlsi/2009 db/conf/glvlsi/glvlsi2009.html#VaisbandGKF09 Asaf Baron Ran Ginosar Isaac Keslassy The Capacity Allocation Paradox. 1359-1367 2009 INFOCOM https://doi.org/10.1109/INFCOM.2009.5062051 conf/infocom/2009 db/conf/infocom/infocom2009.html#BaronGK09 Efraim Rotem Avi Mendelson Ran Ginosar Uri C. Weiser Multiple clock and voltage domains for chip multi processors. 459-468 2009 MICRO https://doi.org/10.1145/1669112.1669170 https://ieeexplore.ieee.org/document/5375435/ conf/micro/2009 db/conf/micro/micro2009.html#RotemMGW09

A. Elyada Ran Ginosar Uri C. Weiser Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. 1243-1248 2008 16 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2008.2000867 db/journals/tvlsi/tvlsi16.html#ElyadaGW08

Rostislav (Reuven) Dobkin Ran Ginosar Fast Universal Synchronizers. 199-208 2008 PATMOS https://doi.org/10.1007/978-3-540-95948-9_20 conf/patmos/2008 db/conf/patmos/patmos2008.html#DobkinG08 Arkadiy Morgenshtein Eby G. Friedman Ran Ginosar Avinoam Kolodny Timing optimization in logic with interconnect. 19-26 2008 SLIP https://doi.org/10.1145/1353610.1353615 https://www.wikidata.org/entity/Q130898254 conf/slip/2008 db/conf/slip/slip2008.html#MorgenshteinFGK08 Rostislav (Reuven) Dobkin Arkadiy Morgenshtein Avinoam Kolodny Ran Ginosar Parallel vs. serial on-chip communication. 43-50 2008 SLIP https://doi.org/10.1145/1353610.1353620 conf/slip/2008 db/conf/slip/slip2008.html#DobkinMKG08

Yevgeny Perelman Ran Ginosar An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection. 130-137 2007 54 IEEE Trans. Biomed. Eng. 1 https://doi.org/10.1109/TBME.2006.883732 https://www.wikidata.org/entity/Q39783915 db/journals/tbe/tbe54.html#PerelmanG07

Rami Rom Jacob Erel Michael Glikson Randy A. Lieberman Kobi Rosenblum Ofer Binah Ran Ginosar David L. Hayes 0001 Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. 542-550 2007 18 IEEE Trans. Neural Networks 2 https://doi.org/10.1109/TNN.2006.890806 https://www.wikidata.org/entity/Q51038716 db/journals/tnn/tnn18.html#RomEGLRBGH07

Zvika Guz Isask'har Walter Evgeny Bolotin Israel Cidon Ran Ginosar Avinoam Kolodny Network Delays and Link Capacities in Application-Specific Wormhole NoCs. 2007 2007 VLSI Design https://doi.org/10.1155/2007/90941 db/journals/vlsi/vlsi2007.html#GuzWBCGK07 90941:1-90941:15

Rostislav (Reuven) Dobkin Yevgeny Perelman Tuvia Liran Ran Ginosar Avinoam Kolodny High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. 3-14 2007 conf/async/2007 ASYNC https://doi.org/10.1109/ASYNC.2007.20 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.20 db/conf/async/async2007.html#DobkinPLGK07 Evgeny Bolotin Israel Cidon Ran Ginosar Avinoam Kolodny Routing table minimization for irregular mesh NoCs. 942-947 2007 conf/date/2007 DATE https://doi.org/10.1109/DATE.2007.364414 https://doi.ieeecomputersociety.org/10.1109/DATE.2007.364414 http://dl.acm.org/citation.cfm?id=1266570 db/conf/date/date2007.html#BolotinCGK07 Evgeny Bolotin Zvika Guz Israel Cidon Ran Ginosar Avinoam Kolodny The Power of Priority: NoC Based Distributed Cache Coherency. 117-126 2007 conf/nocs/2007 NOCS https://doi.org/10.1109/NOCS.2007.42 https://doi.ieeecomputersociety.org/10.1109/NOCS.2007.42 db/conf/nocs/nocs2007.html#BolotinGCGK07 Isask'har Walter Israel Cidon Ran Ginosar Avinoam Kolodny Access Regulation to Hot-Modules in Wormhole NoCs. 137-148 2007 conf/nocs/2007 NOCS https://doi.org/10.1109/NOCS.2007.8 https://doi.ieeecomputersociety.org/10.1109/NOCS.2007.8 db/conf/nocs/nocs2007.html#WalterCGK07 Rostislav (Reuven) Dobkin Ran Ginosar Israel Cidon QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. 218 2007 conf/nocs/2007 NOCS https://doi.org/10.1109/NOCS.2007.36 https://doi.ieeecomputersociety.org/10.1109/NOCS.2007.36 db/conf/nocs/nocs2007.html#DobkinGC07

Uri Frank Tsachy Kapschitz Ran Ginosar A predictive synchronizer for periodic clock domains. 171-186 2006 28 Formal Methods Syst. Des. 2 https://doi.org/10.1007/s10703-006-7843-9 db/journals/fmsd/fmsd28.html#FrankKG06

Yevgeny Perelman Ran Ginosar A low-power inverted ladder D/a converter. 497-501 2006 53-II IEEE Trans. Circuits Syst. II Express Briefs 6 https://doi.org/10.1109/TCSII.2006.875313 db/journals/tcas/tcasII53.html#PerelmanG06

Ilya Obridko Ran Ginosar Minimal Energy Asynchronous Dynamic Adders. 1043-1047 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2006.884056 db/journals/tvlsi/tvlsi14.html#ObridkoG06

Rostislav (Reuven) Dobkin Ran Ginosar Christos P. Sotiriou High Rate Data Synchronization in GALS SoCs. 1063-1074 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 10 https://doi.org/10.1109/TVLSI.2006.884148 db/journals/tvlsi/tvlsi14.html#DobkinGS06

Rostislav (Reuven) Dobkin Ran Ginosar Avinoam Kolodny Fast Asynchronous Shift Register for Bit-Serial Communication. 117-127 2006 conf/async/2006 ASYNC https://doi.org/10.1109/ASYNC.2006.17 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2006.17 db/conf/async/async2006.html#DobkinGK06 Zvika Guz Isask'har Walter Evgeny Bolotin Israel Cidon Ran Ginosar Avinoam Kolodny Efficient link capacity and QoS design for network-on-chip. 9-14 2006 conf/date/2006p DATE https://doi.org/10.1109/DATE.2006.243951 https://doi.ieeecomputersociety.org/10.1109/DATE.2006.243951 http://dl.acm.org/citation.cfm?id=1131487 db/conf/date/date2006p.html#GuzWBCGK06

Rostislav (Reuven) Dobkin Michael Peleg Ran Ginosar Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. 427-438 2005 13 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2004.842916 db/journals/tvlsi/tvlsi13.html#DobkinPG05

Rostislav (Reuven) Dobkin Victoria Vishnyakov Eyal Friedman Ran Ginosar An Asynchronous Router for Multiple Service Levels Networks on Chip. 44-53 2005 conf/async/2005 ASYNC https://doi.org/10.1109/ASYNC.2005.11 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.11 db/conf/async/async2005.html#DobkinVFG05 Tsachy Kapschitz Ran Ginosar Formal Verification of Synchronizers. 359-362 2005 conf/charme/2005 CHARME https://doi.org/10.1007/11560548_31 db/conf/charme/charme2005.html#KapschitzG05 Arkadiy Morgenshtein Israel Cidon Ran Ginosar Avinoam Kolodny Low-leakage repeaters for NoC interconnects. 600-603 2005 conf/iscas/2005 ISCAS (1) https://doi.org/10.1109/ISCAS.2005.1464659 db/conf/iscas/iscas2005-1.html#MorgenshteinCGK05 Ilya Obridko Ran Ginosar Low energy asynchronous architectures. 5238-5241 2005 conf/iscas/2005 ISCAS (5) https://doi.org/10.1109/ISCAS.2005.1465816 db/conf/iscas/iscas2005-5.html#ObridkoG05

Evgeny Bolotin Israel Cidon Ran Ginosar Avinoam Kolodny Cost considerations in network on chip. 19-42 2004 38 Integr. 1 https://doi.org/10.1016/j.vlsi.2004.03.006 db/journals/integration/integration38.html#BolotinCGK04

Evgeny Bolotin Israel Cidon Ran Ginosar Avinoam Kolodny QNoC: QoS architecture and design process for network on chip. 105-128 2004 50 J. Syst. Archit. 2-3 https://doi.org/10.1016/j.sysarc.2003.07.004 db/journals/jsa/jsa50.html#BolotinCGK04

Arkadiy Morgenshtein Michael Moreinis Ran Ginosar Asynchronous gate-diffusion-input (GDI) circuits. 847-856 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2004.831474 db/journals/tvlsi/tvlsi12.html#MorgenshteinMG04

Rostislav (Reuven) Dobkin Ran Ginosar Christos P. Sotiriou Data Synchronization Issues in GALS SoCs. 170-180 2004 conf/async/2004 ASYNC https://doi.org/10.1109/ASYNC.2004.1299298 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2004.1299298 db/conf/async/async2004.html#DobkinGS04 Alex Branover Rakefet Kol Ran Ginosar Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. 870-877 2004 conf/date/2004 DATE https://doi.org/10.1109/DATE.2004.1268996 https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268996 http://dl.acm.org/citation.cfm?id=969197 db/conf/date/date2004-2.html#BranoverKG04 Ilya Obridko Ran Ginosar Low energy asynchronous adders. 164-167 2004 ICECS https://doi.org/10.1109/ICECS.2004.1399640 conf/icecsys/2004 db/conf/icecsys/icecsys2004.html#ObridkoG04 Evgeny Bolotin Arkadiy Morgenshtein Israel Cidon Ran Ginosar Avinoam Kolodny Automatic hardware-efficient SoC integration by QoS network on chip. 479-482 2004 ICECS https://doi.org/10.1109/ICECS.2004.1399722 conf/icecsys/2004 db/conf/icecsys/icecsys2004.html#BolotinMCGK04 Arkadiy Morgenshtein Evgeny Bolotin Israel Cidon Avinoam Kolodny Ran Ginosar Micro-modem - reliability solution for NoC communications. 483-486 2004 ICECS https://doi.org/10.1109/ICECS.2004.1399723 conf/icecsys/2004 db/conf/icecsys/icecsys2004.html#MorgenshteinBCKG04 Arkadiy Morgenshtein Israel Cidon Avinoam Kolodny Ran Ginosar Comparative analysis of serial vs parallel links in NoC. 185-188 2004 SoC https://doi.org/10.1109/ISSOC.2004.1411181 conf/issoc/2004 db/conf/issoc/issoc2004.html#MorgenshteinCKG04 Uri Frank Ran Ginosar A Predictive Synchronizer for Periodic Clock Domains. 402-412 https://doi.org/10.1007/978-3-540-30205-6_42 2004 conf/patmos/2004 PATMOS db/conf/patmos/patmos2004.html#FrankG04

Ken S. Stevens Ran Ginosar Shai Rotem Relative timing [asynchronous design]. 129-140 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2002.801606 db/journals/tvlsi/tvlsi11.html#StevensGR03

Y. Elboim Avinoam Kolodny Ran Ginosar A clock-tuning circuit for system-on-chip. 616-626 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2003.812371 db/journals/tvlsi/tvlsi11.html#ElboimKG03

Yaron Semiat Ran Ginosar Timing Measurements of Synchronization Circuits. 68-77 2003 conf/async/2003 ASYNC https://doi.org/10.1109/ASYNC.2003.1199167 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2003.1199167 db/conf/async/async2003.html#SemiatG03 Ran Ginosar Fourteen Ways to Fool Your Synchronizer. 89-97 2003 conf/async/2003 ASYNC https://doi.org/10.1109/ASYNC.2003.1199169 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2003.1199169 db/conf/async/async2003.html#Ginosar03 Rostislav (Reuven) Dobkin Michael Peleg Ran Ginosar Parallel VLSI architecture for MAP turbo decoder. 384-388 2002 PIMRC https://doi.org/10.1109/PIMRC.2002.1046727 conf/pimrc/2002 db/conf/pimrc/pimrc2002.html#DobkinPG02

Kenneth S. Stevens Shai Rotem Ran Ginosar Peter A. Beerel Chris J. Myers Kenneth Y. Yun Rakefet Kol Charles Dike Marly Roncken An asynchronous instruction length decoder. 217-228 2001 36 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/4.902762 https://www.wikidata.org/entity/Q59859603 db/journals/jssc/jssc36.html#StevensRGBMYKDR01

Yevgeny Perelman Ran Ginosar A low-light-level sensor for medical diagnostic applications. 1553-1558 2001 36 IEEE J. Solid State Circuits 10 https://doi.org/10.1109/4.953484 db/journals/jssc/jssc36.html#PerelmanG01

Shai Rotem Ken S. Stevens Charles Dike Marly Roncken Boris Agapiev Ran Ginosar Rakefet Kol Peter A. Beerel Chris J. Myers Kenneth Y. Yun RAPPID: An Asynchronous Instruction Length Decoder. 60-70 1999 conf/async/1999 ASYNC https://doi.org/10.1109/ASYNC.1999.761523 https://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761523 https://www.wikidata.org/entity/Q59859625 db/conf/async/async1999.html#RotemSDRAGKBMY99 Ken S. Stevens Shai Rotem Ran Ginosar Relative Timing. 208-218 1999 conf/async/1999 ASYNC https://doi.org/10.1109/ASYNC.1999.761535 https://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761535 db/conf/async/async1999.html#StevensRG99 Ken S. Stevens Shai Rotem Steven M. Burns Jordi Cortadella Ran Ginosar Michael Kishinevsky Marly Roncken CAD Directions for High Performance Asynchronous Circuits. 116-121 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309893 https://www.wikidata.org/entity/Q56892870 db/conf/dac/dac99.html#StevensRBCGKR99

Stuart G. Wolf Ran Ginosar Yehoshua Y. Zeevi Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing. 25-37 1998 9 J. Vis. Commun. Image Represent. 1 https://doi.org/10.1006/jvci.1998.0371 db/journals/jvcir/jvcir9.html#WolfGZ98

Wei-Chun Chou Peter A. Beerel Ran Ginosar Rakefet Kol Chris J. Myers Shai Rotem Ken S. Stevens Kenneth Y. Yun Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. 80- 1998 conf/async/1998 ASYNC https://doi.org/10.1109/ASYNC.1998.666496 https://doi.ieeecomputersociety.org/10.1109/ASYNC.1998.666496 db/conf/async/async1998.html#ChouBGKMRSY98 Ran Ginosar Rakefet Kol Adaptive synchronization. 188-189 1998 conf/iccd/1998 ICCD https://doi.org/10.1109/ICCD.1998.727042 https://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727042 db/conf/iccd/iccd1998.html#GinosarK98 Rakefet Kol Ran Ginosar <i>Kin</i>: A High Performance Asynchronous Processor Architecture. 433-440 1998 conf/ics/1998 International Conference on Supercomputing https://doi.org/10.1145/277830.277937 db/conf/ics/ics1998.html#KolG98 Uzi Zangi Ran Ginosar A low power video processor. 136-138 1998 conf/islped/1998 ISLPED https://doi.org/10.1145/280756.280835 db/conf/islped/islped1998.html#ZangiG98 Rakefet Kol Ran Ginosar A Double-Latched Asynchronous Pipeline. 706-712 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#KolG97 https://doi.org/10.1109/ICCD.1997.628942 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628942 Rakefet Kol Ran Ginosar Goel Samuel Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. 164-174 1996 ASYNC https://doi.org/10.1109/ASYNC.1996.494448 https://doi.ieeecomputersociety.org/10.1109/ASYNC.1996.494448 conf/async/1996 db/conf/async/async1996.html#KolGS96

Ilana David Ran Ginosar Michael Yoeli Self-timed is self-checking. 219-228 1995 6 J. Electron. Test. 2 https://doi.org/10.1007/BF00993088 db/journals/et/et6.html#DavidGY95

Sarit Chen Ran Ginosar Adaptive sensitivity CCD image sensor. 363-365 1994 ICPR (3) https://doi.org/10.1109/ICPR.1994.577203 https://doi.ieeecomputersociety.org/10.1109/ICPR.1994.577203 conf/icpr/1994-3 db/conf/icpr/icpr1994-3.html#ChenG94 Stuart G. Wolf Ran Ginosar Yehoshua Y. Zeevi Spatio-chromatic model for colour image processing. 599-601 1994 ICPR (1) https://doi.org/10.1109/ICPR.1994.576372 https://doi.ieeecomputersociety.org/10.1109/ICPR.1994.576372 conf/icpr/1994-1 db/conf/icpr/icpr1994-1.html#WolfGZ94

Alan Rotman Ran Ginosar Control unit synthesis from a high-level language. 162-167 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.184853 db/journals/tcad/tcad12.html#RotmanG93

Ilana David Ran Ginosar Michael Yoeli Self-Timed Architecture of a Reduced Instruction Set Computer. 29-43 1993 conf/ifip10-5/1993 Asynchronous Design Methodologies db/conf/ifip10-5/ifip10-5-1993.html#DavidGY93

Ilana David Ran Ginosar Michael Yoeli An Efficient Implementation of Boolean Functions as Self-Timed Circuits. 2-11 1992 41 IEEE Trans. Computers 1 db/journals/tc/tc41.html#DavidGY92 https://doi.org/10.1109/12.123377 http://doi.ieeecomputersociety.org/10.1109/12.123377

Ilana David Ran Ginosar Michael Yoeli Implementing Sequential Machines as Self-Timed Circuits. 12-17 1992 41 IEEE Trans. Computers 1 db/journals/tc/tc41.html#DavidGY92a https://doi.org/10.1109/12.123378 http://doi.ieeecomputersociety.org/10.1109/12.123378

Arie Harsat Ran Ginosar CARMEL-4: The Unify-Spawn Machine for FCP. 840-854 1991 conf/iclp/1991 ICLP db/conf/iclp/iclp91.html#HarsatG91

Arie Harsat Ran Ginosar CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. 197-218 1990 7 New Gener. Comput. 2-3 https://doi.org/10.1007/BF03037206 db/journals/ngc/ngc7.html#HarsatG90

Ran Ginosar Nick Michell On the potential of asynchronous pipelined processors. 27-34 1990 18 SIGARCH Comput. Archit. News 4 https://doi.org/10.1145/121973.121977 db/journals/sigarch/sigarch18.html#GinosarM90

Arie Harsat Ran Ginosar An Extended RISC Methodology and its Application to FCP. 67-82 1990 conf/iclp/1990 ICLP db/conf/iclp/iclp90.html#HarsatG90 Yehoshua Y. Zeevi Ran Ginosar Foveating vision systems architecture: image acquisition and display. 1990 VCIP https://doi.org/10.1117/12.24224 conf/vcip/1990 db/conf/vcip/vcip1990.html#ZeeviG90

Ran Ginosar David Egozi Topological comparison of perfect shuffle and hypercube. 37-68 1989 18 Int. J. Parallel Program. 1 https://doi.org/10.1007/BF01409745 db/journals/ijpp/ijpp18.html#GinosarE89

Llana David Ran Ginosar Michael Yoeli An efficient implementation of Boolean functions nd finite state machine as self-timed circuit. 91-104 1989 17 SIGARCH Comput. Archit. News 6 https://doi.org/10.1145/77254.77262 https://www.wikidata.org/entity/Q130951289 db/journals/sigarch/sigarch17.html#DavidGY89

Arie Harsat Ran Ginosar CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. 962-969 1988 conf/fgcs/1988 FGCS db/conf/fgcs/fgcs88.html#HarsatG88 Ran Ginosar Dwight D. Hill Design and Implementation of Switching Systems for Parallel Processors. 674-680 1985 conf/icpp/1985 ICPP db/conf/icpp/icpp1985.html#GinosarH85 Bruce W. Arden Ran Ginosar Performance evaluation of the MP/C. 539-555 1983 AFIPS National Computer Conference https://doi.org/10.1145/1500676.1500744 conf/afips/1983 db/conf/afips/ncc83.html#ArdenG83

Bruce W. Arden Ran Ginosar MP/C: A Multiprocessor/Computer Architecture. 455-473 1982 31 IEEE Trans. Computers 5 db/journals/tc/tc31.html#ArdenG82 https://doi.org/10.1109/TC.1982.1676022 http://doi.ieeecomputersociety.org/10.1109/TC.1982.1676022

Bruce W. Arden Ran Ginosar MP/C: A Multiprocessor/Computer Architecture. 3-20 1981 conf/isca/1981 ISCA db/conf/isca/isca81.html#ArdenG81 http://dl.acm.org/citation.cfm?id=801863 Bruce W. Arden Ran Ginosar A Single-Relation Module for a Data Base Machine. 227-238 1981 conf/isca/1981 ISCA db/conf/isca/isca81.html#ArdenG81a http://dl.acm.org/citation.cfm?id=801878 Ameer Abdelhadi Boris Agapiev Yoni Aizik Nils Albartus Bruce W. Arden Itai Avron Leonid Azriel Asaf Baron Salomon Beer Peter A. Beerel Yosi Ben-Asher Amit Berman Ofer Binah Evgeny Bolotin Alex Branover Steven M. Burns Marco Cannizzaro Tom Chaney Karam S. Chatha Sarit Chen Wei-Chun Chou Israel Cidon Jordi Cortadella Jerome Cox Ilana David Llana David Ron Diamant Charles Dike Rostislav (Reuven) Dobkin David Egozi Y. Elboim A. Elyada Jacob Erel Mattan Erez João Dinis Ferreira Uri Frank Eby G. Friedman Eyal Friedman Michael Glikson Shay Gueron Zvika Guz Jawad Haj-YahyaJawad Haj-Yihia Arie Harsat David L. Hayes 0001 Dwight D. Hill Roman Kaplan Tsachy Kapschitz Idit Keidar Isaac Keslassy Michael Kishinevsky Rakefet Kol Avinoam Kolodny Shahar Kvatinsky Luciano Lavagno Randy A. Lieberman Tuvia Liran Suyash Mahar Radu Marculescu Avi Mendelson Nick Michell Amir Morad Tomer Y. Morad Michael Moreinis Arkadiy Morgenshtein Michael Moyal Onur Mutlu Chris J. Myers Danniel Nahmanny Eyal-Itzhak Nave Ilya Obridko Lois Orosa 0001 Christof Paar Inna Partin-VaisbandInna Vaisband Michael Peleg Yevgeny Perelman Michael Priel Misbah Ramadan Rami Rom Marly Roncken Kobi Rosenblum Efraim Rotem Shai Rotem Alan Rotman Goel Samuel Yaron Semiat Christos P. Sotiriou Julian Speith Kenneth S. StevensKen S. Stevens Aharon Unikovski Dmitri Vainbrand Dmitry Verbitsky Victoria Vishnyakov Nicolás Wainstein Isask'har Walter Uri C. Weiser Eliezer Weissmann Yoav Weizman Stuart G. Wolf Ahmad Yasin Leonid Yavits Michael Yoeli Kenneth Y. Yun Uzi Zangi David M. Zar Yehoshua Y. Zeevi Y. Zhang