Gate Delay Estimation in STA under Dynamic Power Supply Noise.

Kenji Shimazaki

Takaaki Okumura Fumihiro Minami Kenji Shimazaki Kimihiko Kuwada Masanori Hashimoto Gate Delay Estimation in STA under Dynamic Power Supply Noise. 2447-2455 2010 93-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1587/transfun.E93.A.2447 http://search.ieice.org/bin/summary.php?id=e93-a_12_2447 db/journals/ieicet/ieicet93a.html#OkumuraMSKH10

Takaaki Okumura Fumihiro Minami Kenji Shimazaki Kimihiko Kuwada Masanori Hashimoto Gate delay estimation in STA under dynamic power supply noise. 775-780 2010 ASP-DAC https://doi.org/10.1109/ASPDAC.2010.5419786 http://dl.acm.org/citation.cfm?id=1899899 conf/aspdac/2010 db/conf/aspdac/aspdac2010.html#OkumuraMSKH10 Kenji Shimazaki Takaaki Okumura A minimum decap allocation technique based on simultaneous switching for nanoscale SoC. 21-24 2009 CICC https://doi.org/10.1109/CICC.2009.5280916 conf/cicc/2009 db/conf/cicc/cicc2009.html#ShimazakiO09

Kenji Shimazaki Makoto Nagata Mitsuya Fukazawa Shingo Miyahara Masaaki Hirata Kazuhiro Satoh Hiroyuki Tsujikawa An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. 1535-1543 2006 89-C IEICE Trans. Electron. 11 https://doi.org/10.1093/ietele/e89-c.11.1535 db/journals/ieicet/ieicet89c.html#ShimazakiNFMHST06

Kenji Shimazaki Makoto Nagata Takeshi Okumoto Shozo Hirano Hiroyuki Tsujikawa Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. 589-596 2005 88-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e88-c.4.589 db/journals/ieicet/ieicet88c.html#ShimazakiNOHT05

Hiroyuki Tsujikawa Kenji Shimazaki Shozo Hirano Kazuhiro Sato Masanori Hirofuji Junichi Shimada Mitsumi Ito Kiyohito Mukai Power-Supply Noise Reduction with Design for Manufacturability. 3421-3428 2005 88-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e88-a.12.3421 db/journals/ieicet/ieicet88a.html#TsujikawaSHSHSIM05

Kenji Shimazaki Mitsuya Fukazawa Makoto Nagata Shingo Miyahara Masaaki Hirata Kazuhiro Satoh Hiroyuki Tsujikawa An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. 31-34 2005 CICC https://doi.org/10.1109/CICC.2005.1568600 conf/cicc/2005 db/conf/cicc/cicc2005.html#ShimazakiFNMHST05 Yoshihide Komatsu Koichiro Ishibashi Masaharu Yamamoto Toshiro Tsukada Kenji Shimazaki Mitsuya Fukazawa Makoto Nagata Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. 35-38 2005 CICC https://doi.org/10.1109/CICC.2005.1568601 conf/cicc/2005 db/conf/cicc/cicc2005.html#KomatsuIYTSFN05 Shen Lin Makoto Nagata Kenji Shimazaki Kazuhiro Satoh Masaya Sumita Hiroyuki Tsujikawa Andrew T. Yang Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. 509-512 2004 CICC https://doi.org/10.1109/CICC.2004.1358869 conf/cicc/2004 db/conf/cicc/cicc2004.html#LinNSSSTY04

Hiroyuki Tsujikawa Shozo Hirano Kenji Shimazaki A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation. 2974-2982 2003 86-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 http://search.ieice.org/bin/summary.php?id=e86-a_12_2974 db/journals/ieiceta/ieiceta86.html#TsujikawaHS03

Wen Kung Chu Nishath K. Verghese Heayn-Jun Chol Kenji Shimazaki Hiroyuki Tsujikawa Shouzou Hirano Shirou Doushoh Makoto Nagata Atsushi Iwata Takafumi Ohmoto A substrate noise analysis methodology for large-scale mixed-signal ICs. 369-372 2003 CICC https://doi.org/10.1109/CICC.2003.1249420 conf/cicc/2003 db/conf/cicc/cicc2003.html#ChuVCSTHDNIO03 Hiroyulu Tsujikawa Kenji Shimazaki Shozo Hirano Motohiro Ohki Talcashi Yoneda Hiroshi Benno A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification. 299-302 2002 CICC https://doi.org/10.1109/CICC.2002.1012822 conf/cicc/2002 db/conf/cicc/cicc2002.html#TsujikawaSHOYB02 Kenji Shimazaki Shouzou Hirano Hiroyuki Tsujikawa An EMI-Noise Analysis on LSI Design with Impedance Estimation. 169-174 2002 conf/isqed/2002 ISQED https://doi.org/10.1109/ISQED.2002.996724 https://doi.ieeecomputersociety.org/10.1109/ISQED.2002.996724 db/conf/isqed/isqed2002.html#ShimazakiHT02 Kenji Shimazaki Hiroyuki Tsujikawa Seijiro Kojima Shouzou Hirano LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. 129-136 2000 conf/isqed/2000 ISQED https://doi.org/10.1109/ISQED.2000.838865 https://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838865 db/conf/isqed/isqed2000.html#ShimazakiTKH00 Hiroshi Benno Heayn-Jun Chol Wen Kung Chu Shirou Doushoh Mitsuya Fukazawa Masanori Hashimoto Shouzou Hirano Shozo Hirano Masaaki Hirata Masanori Hirofuji Koichiro Ishibashi Mitsumi Ito Atsushi Iwata Seijiro Kojima Yoshihide Komatsu Kimihiko Kuwada Shen Lin Fumihiro Minami Shingo Miyahara Kiyohito Mukai Makoto Nagata Motohiro Ohki Takafumi Ohmoto Takeshi Okumoto Takaaki Okumura Kazuhiro Sato Kazuhiro Satoh Junichi Shimada Masaya Sumita Hiroyuki Tsujikawa Hiroyulu Tsujikawa Toshiro Tsukada Nishath K. Verghese Masaharu Yamamoto Andrew T. Yang Talcashi Yoneda