Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving.

Kazutami Arimoto Hiroshi Miyata Kazutami Arimoto Masatoshi Saitoh Atsushi Hayami Hisayoshi Mizuno Yukihiko Shimazu Tomoyuki Yokogawa Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving. 595-600 2024 IIAI-AAI https://doi.org/10.1109/IIAI-AAI63651.2024.00113 conf/iiaiaai/2024 db/conf/iiaiaai/iiaiaai2024.html#MiyataASHMSY24 Ryugo Tanaka Tomoyuki Yokogawa Sousuke Amasaki Hirohisa Aman Kazutami Arimoto Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints. 881-884 2023 GCCE https://doi.org/10.1109/GCCE59613.2023.10315312 conf/gcce/2023 db/conf/gcce/gcce2023.html#TanakaYAAA23 Tomoya Kubo Tomoyuki Yokogawa Kazutami Arimoto Masaki Hokari Isao Kayano Enhancing the Generalization Performance of Drowsiness Estimation AI in Drivers Using Time-Series Data from FAUs with Limited Datasets. 165-170 2023 IIAI-AAI-Winter https://doi.org/10.1109/IIAI-AAI-Winter61682.2023.00039 conf/iiaiaai/2023winter db/conf/iiaiaai/iiaiaai2023winter.html#KuboYAHK23 Kazuma Toyota Tomoyuki Yokogawa Sousuke Amasaki Hirohisa Aman Kazutami Arimoto A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users. 684-685 2022 IIAI-AAI https://doi.org/10.1109/IIAIAAI55812.2022.00142 conf/iiaiaai/2022 db/conf/iiaiaai/iiaiaai2022.html#ToyotaYAAA22 Kazuki Wayama Tomoyuki Yokogawa Sousuke Amasaki Hirohisa Aman Kazutami Arimoto Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking. 213:1-213:8 2022 ASE https://doi.org/10.1145/3551349.3560505 https://www.wikidata.org/entity/Q130838845 conf/kbse/2022 db/conf/kbse/ase2022.html#WayamaYAAA22 Yuji Yano Hisashi Iwamoto Takuma Yoshimura Yoshihiro Nishida Tatsuya Mori Kiyotaka Komoku Hidekuni Takao Kazutami Arimoto 28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. 1-4 2022 VLSI-DAT https://doi.org/10.1109/VLSI-DAT54769.2022.9768071 conf/vlsi-dat/2022 db/conf/vlsi-dat/vlsi-dat2022.html#YanoIYNMKTA22 Hidekuni Takao Kazuki Watatani Kazutami Arimoto New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability. 1-36 2021 HCS https://doi.org/10.1109/HCS52781.2021.9567179 conf/hotchips/2021 db/conf/hotchips/hotchips2021.html#TakaoWA21 Hiroshi Miyata Kazutami Arimoto Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area. 1-6 2021 ICC Workshops https://doi.org/10.1109/ICCWorkshops50388.2021.9473632 conf/icc/2021w db/conf/icc/icc2021w.html#MiyataA21

Nao Igawa Tomoyuki Yokogawa Sousuke Amasaki Masafumi Kondo Yoichiro Sato Kazutami Arimoto Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking. 702-705 2020 103-D IEICE Trans. Inf. Syst. 3 http://search.ieice.org/bin/summary.php?id=e103-d_3_702 https://doi.org/10.1587/transinf.2019EDL8086 db/journals/ieicetd/ieicetd103.html#IgawaYAKSA20

Hayato Naito Tomoyuki Yokogawa Nao Igawa Sousuke Amasaki Hirohisa Aman Kazutami Arimoto A Node-Style Visual Programming Environment for the nuXmv Model Checker. 71-75 2020 GCCE https://doi.org/10.1109/GCCE50665.2020.9291945 conf/gcce/2020 db/conf/gcce/gcce2020.html#NaitoYIAAA20 Tomoki Kobayashi Tomoyuki Yokogawa Nao Igawa Yoichiro Sato Kimihoro Sugino Hiroshi Miyata Satoshi Fujii Kazutami Arimoto A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management. 404-407 2020 IIAI-AAI https://doi.org/10.1109/IIAI-AAI50415.2020.00088 conf/iiaiaai/2020 db/conf/iiaiaai/iiaiaai2020.html#KobayashiYISSMF20 Nao Igawa Tomoyuki Yokogawa Mami Takahashi Kazutami Arimoto Model Checking of Visual Scripts Created by UE4 Blueprints. 512-515 2020 IIAI-AAI https://doi.org/10.1109/IIAI-AAI50415.2020.00107 conf/iiaiaai/2020 db/conf/iiaiaai/iiaiaai2020.html#IgawaYTA20 Satoshi Fujii Issei Nakaema Kei Miyagi Shouichiro Tanifuji Noriaki Yoshikawa Kensaku Kinoshita Kazutami Arimoto Radio link design for ITS integrated network using drone. 1-4 2019 APWCS https://doi.org/10.1109/VTS-APWCS.2019.8851623 conf/apwcs2/2019 db/conf/apwcs2/apwcs2019.html#FujiiNMTYKA19 Akira Matsumoto Tomoyuki Yokogawa Sousuke Amasaki Hirohisa Aman Kazutami Arimoto Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks. 458-461 2019 IIAI-AAI https://doi.org/10.1109/IIAI-AAI.2019.00100 conf/iiaiaai/2019 db/conf/iiaiaai/iiaiaai2019.html#MatsumotoYAAA19 Tomoki Kobayashi Tomoyuki Yokogawa Nao Igawa Yoichiro Sato Satoshi Fujii Kazutami Arimoto A Compact Low Power AI Module Mounted on Drone for Plant Monitor System. 1081-1082 2019 IIAI-AAI https://doi.org/10.1109/IIAI-AAI.2019.00236 conf/iiaiaai/2019 db/conf/iiaiaai/iiaiaai2019.html#KobayashiYISFA19 Nao Igawa Tomoyuki Yokogawa Sousuke Amasaki Kiyotaka Komoku Yoichiro Sato Kazutami Arimoto Interpolation Based Unbounded Model Checking for Time Petri Nets. 619-623 2018 GCCE https://doi.org/10.1109/GCCE.2018.8574651 conf/gcce/2018 db/conf/gcce/gcce2018.html#IgawaYAKSA18 Kazutami Arimoto Daichi Yamashita Nao Igawa Tomoyuki Yokogawa Yoichiro Sato Isao Kayano Akio Shiratori A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. 63-64 2017 ISOCC https://doi.org/10.1109/ISOCC.2017.8368828 conf/isocc/2017 db/conf/isocc/isocc2017.html#ArimotoYIYSKS17 Salilthip Phuklang Tomoyuki Yokogawa Pattara Leelaprute Kazutami Arimoto Tool Support for Consistency Verification of UML Diagrams. 606-609 2017 PROFES https://doi.org/10.1007/978-3-319-69926-4_51 conf/profes/2017 db/conf/profes/profes2017.html#PhuklangYLA17

Yoshifumi Kawamura Naoya Okada Yoshio Matsuda Tetsuya Matsumura Hiroshi Makino Kazutami Arimoto A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. 917-928 2016 99-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 5 https://doi.org/10.1587/transfun.E99.A.917 http://search.ieice.org/bin/summary.php?id=e99-a_5_917 db/journals/ieicet/ieicet99a.html#KawamuraOMMMA16

Daichi Okamoto Masafumi Kondo Tomoyuki Yokogawa Yoshihiro Sejima Kazutami Arimoto Yoichiro Sato A Serial Booth Multiplier Using Ring Oscillator. 458-461 2016 CANDAR https://doi.org/10.1109/CANDAR.2016.0086 https://doi.ieeecomputersociety.org/10.1109/CANDAR.2016.0086 conf/ic-nc/2016 db/conf/ic-nc/candar2016.html#OkamotoKYSAS16 Kiyotaka Komoku Kazutami Arimoto Tomoyuki Yokogawa Hitoshi Yamauchi Yoichiro Sato Hidekuni Takao 3D<sup>2</sup> processing architecture - High reliability and low power computing for novel nano tactile sensor array. 199-200 2016 ISOCC https://doi.org/10.1109/ISOCC.2016.7799856 conf/isocc/2016 db/conf/isocc/isocc2016.html#KomokuAYYST16

Tomoyuki Yokogawa Masafumi Kondo Hisashi Miyazaki Sousuke Amasaki Yoichiro Sato Kazutami Arimoto Bounded model checking of Time Petri Nets using SAT solver. 20141112 2015 12 IEICE Electron. Express 2 https://doi.org/10.1587/elex.11.20141112 db/journals/ieiceee/ieiceee12.html#YokogawaKMASA15

Tetsuya Matsumura Naoya Okada Yoshifumi Kawamura Koji Nii Kazutami Arimoto Hiroshi Makino Yoshio Matsuda The LSI implementation of a memory based field programmable device for MCU peripherals. 183-188 2014 DDECS https://doi.org/10.1109/DDECS.2014.6868787 https://doi.ieeecomputersociety.org/10.1109/DDECS.2014.6868787 conf/ddecs/2014 db/conf/ddecs/ddecs2014.html#MatsumuraOKNAMM14 Woogeun Rhee Gangadhar Burra Kazutami Arimoto Pieter Harpe Brian Otis David Ruffieux F5: Low-power radios for sensor networks. 518-519 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757544 conf/isscc/2014 db/conf/isscc/isscc2014.html#RheeBAHOR14

Kazuhiro Ueda Fukashi Morishita Shunsuke Okura Leona Okamura Tsutomu Yoshihara Kazutami Arimoto Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. 2608-2617 2013 48 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2013.2274829 db/journals/jssc/jssc48.html#UedaMOOYA13

Tomoyuki Yokogawa Sousuke Amasaki Keisuke Okazaki Yoichiro Sato Kazutami Arimoto Hisashi Miyazaki Consistency Verification of UML Diagrams Based on Process Bisimulation. 126-127 2013 PRDC https://doi.org/10.1109/PRDC.2013.25 https://doi.ieeecomputersociety.org/10.1109/PRDC.2013.25 conf/prdc/2013 db/conf/prdc/prdc2013.html#YokogawaAOSAM13 Kazutami Arimoto Sam Kavusi Kenneth Salisbury What's next in robots? ∼Sensing, processing, networking toward human brain and body. 514 2012 ISSCC https://doi.org/10.1109/ISSCC.2012.6177109 conf/isscc/2012 db/conf/isscc/isscc2012.html#ArimotoKS12

Toru Shimizu Kazutami Arimoto Osamu Nishii Sugako Otani Hiroyuki Kondo Low Power Platform for Embedded Processor LSIs. 394-400 2011 94-C IEICE Trans. Electron. 4 https://doi.org/10.1587/transele.E94.C.394 http://search.ieice.org/bin/summary.php?id=e94-c_4_394 db/journals/ieicet/ieicet94c.html#ShimizuANOK11

Takashi Kurafuji Masaru Haraguchi Masami Nakajima Tetsu Nishijima Tetsushi Tanizaki Hiroyuki Yamasaki Takeaki Sugimura Yuta Imai Masakatsu Ishizaki Takeshi Kumaki Kan Murata Kanako Yoshida Eisuke Shimomura Hideyuki Noda Yoshihiro Okuno Shunsuke Kamijo Tetsushi Koide Hans Jürgen Mattausch Kazutami Arimoto A Scalable Massively Parallel Processor for Real-Time Image Processing. 2363-2373 2011 46 IEEE J. Solid State Circuits 10 https://doi.org/10.1109/JSSC.2011.2159528 db/journals/jssc/jssc46.html#KurafujiHNNTYSIIKMYSNOKKMA11

Sugako Otani Hiroyuki Kondo Itaru Nonomura Atsuyuki Ikeya Minoru Uemura Katsushi Asahina Kazutami Arimoto Shin'ichi Miura Toshihiro Hanawa Taisuke Boku Mitsuhisa Sato An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. 1-3 2011 COOL Chips https://doi.org/10.1109/COOLCHIPS.2011.5890920 conf/coolchips/2011 db/conf/coolchips/coolchips2011.html#OtaniKNIUAAMHBS11 Yushi Moko Yoshihiro Watanabe Takashi Komuro Masatoshi Ishikawa Masami Nakajima Kazutami Arimoto Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. 157-162 2011 CVPR Workshops https://doi.org/10.1109/CVPRW.2011.5981839 https://doi.ieeecomputersociety.org/10.1109/CVPRW.2011.5981839 conf/cvpr/2011w db/conf/cvpr/cvprw2011.html#MokoWKINA11 Toshihiro Hanawa Taisuke Boku Shin'ichi Miura Mitsuhisa Sato Kazutami Arimoto PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. 871-879 2011 IPDPS Workshops https://doi.org/10.1109/IPDPS.2011.232 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2011.232 conf/ipps/2011w db/conf/ipps/ipdps2011w.html#HanawaBMSA11 Sugako Otani Hiroyuki Kondo Itaru Nonomura Atsuyuki Ikeya Minoru Uemura Yasushi Hayakawa Takeshi Oshita Satoshi Kaneko Katsushi Asahina Kazutami Arimoto Shin'ichi Miura Toshihiro Hanawa Taisuke Boku Mitsuhisa Sato An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. 266-268 2011 ISSCC https://doi.org/10.1109/ISSCC.2011.5746312 conf/isscc/2011 db/conf/isscc/isscc2011.html#OtaniKNIUHOKAAMHBS11 Toshihiro Hanawa Taisuke Boku Shin'ichi Miura Mitsuhisa Sato Kazutami Arimoto PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. 284-291 2010 GreenCom/CPSCom https://doi.org/10.1109/GreenCom-CPSCom.2010.115 https://doi.ieeecomputersociety.org/10.1109/GreenCom-CPSCom.2010.115 conf/greencom/2010 db/conf/greencom/greencom2010.html#HanawaBMSA10 Takashi Kurafuji Masaru Haraguchi Masami Nakajima Takayuki Gyohten Tetsu Nishijima Hiroyuki Yamasaki Yuta Imai Masakatsu Ishizaki Takeshi Kumaki Yoshihiro Okuno Tetsushi Koide Hans Jürgen Mattausch Kazutami Arimoto A scalable massively parallel processor for real-time image processing. 334-335 2010 ISSCC https://doi.org/10.1109/ISSCC.2010.5433910 conf/isscc/2010 db/conf/isscc/isscc2010.html#KurafujiHNGNYIIKOKMA10 Satoshi Shigematsu Kazutami Arimoto Christoph Hagleitner Fusion of MEMS and circuits. 526-527 2010 ISSCC https://doi.org/10.1109/ISSCC.2010.5433878 conf/isscc/2010 db/conf/isscc/isscc2010.html#ShigematsuAH10 Koji Nii Makoto Yabuuchi Hidehiro Fujiwara Hirofumi Nakano Kazuya Ishihara Hiroyuki Kawai Kazutami Arimoto Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. 519-524 2010 SoCC https://doi.org/10.1109/SOCC.2010.5784684 conf/socc/2010 db/conf/socc/socc2010.html#NiiYFNIKA10

Hiroki Shimano Fukashi Morishita Katsumi Dosaka Kazutami Arimoto On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. 356-363 2009 92-C IEICE Trans. Electron. 3 https://doi.org/10.1587/transele.E92.C.356 http://search.ieice.org/bin/summary.php?id=e92-c_3_356&category=C&year=2009&lang=E&abst= db/journals/ieicet/ieicet92c.html#ShimanoMDA09

Masaru Haraguchi Tokuya Osawa Akira Yamazaki Chikayoshi Morishima Toshinori Morihara Yoshikazu Morooka Yoshihiro Okuno Kazutami Arimoto A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. 453-459 2009 92-C IEICE Trans. Electron. 4 https://doi.org/10.1587/transele.E92.C.453 http://search.ieice.org/bin/summary.php?id=e92-c_4_453&category=C&year=2009&lang=E&abst= db/journals/ieicet/ieicet92c.html#HaraguchiOYMMMOA09

Hiroyuki Kondo Sugako Otani Masami Nakajima Osamu Yamamoto Norio Masui Naoto Okumura Mamoru Sakugawa Masaya Kitao Koichi Ishimi Masayuki Sato Fumitaka Fukuzawa Satoshi Imasu Nobuhiro Kinoshita Yusuke Ota Kazutami Arimoto Toru Shimizu Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. 2251-2259 2009 44 IEEE J. Solid State Circuits 8 https://doi.org/10.1109/JSSC.2009.2022219 db/journals/jssc/jssc44.html#KondoONYMOSKISF09

Takeshi Kumaki Masakatsu Ishizaki Tetsushi Koide Hans Jürgen Mattausch Yasuto Kuroda Takayuki Gyohten Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Kazunori Saito Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. 1409-1418 2008 91-C IEICE Trans. Electron. 9 https://doi.org/10.1093/ietele/e91-c.9.1409 db/journals/ieicet/ieicet91c.html#KumakiIKMKGNDAS08

Hiroyuki Kondo Masami Nakajima Norio Masui Sugako Otani Naoto Okumura Yukari Takata Takashi Nasu Hirokazu Takata Takashi Higuchi Mamoru Sakugawa Hayato Fujiwara Kazuya Ishida Koichi Ishimi Satoshi Kaneko Teruyuki Itoh Masayuki Sato Osamu Yamamoto Kazutami Arimoto Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. 892-901 2008 43 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2008.917528 db/journals/jssc/jssc43.html#KondoNMOOTNTHSF08

Hiroyuki Kondo Masami Nakajima Sugako Otani Osamu Yamamoto Norio Masui Naoto Okumura Mamoru Sakugawa Masaya Kitao Koichi Ishimi Masayuki Sato Fumitaka Fukuzawa Kazuhiro Inaoka Yoshihiro Saito Kazutami Arimoto Toru Shimizu Heterogeneous multicore SoC for secure multimedia applications. 675-678 2008 CICC https://doi.org/10.1109/CICC.2008.4672175 conf/cicc/2008 db/conf/cicc/cicc2008.html#KondoNOYMOSKISFISAS08

Takeshi Kumaki Yasuto Kuroda Masakatsu Ishizaki Tetsushi Koide Hans Jürgen Mattausch Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Kazunori Saito Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. 334-345 2007 90-D IEICE Trans. Inf. Syst. 1 https://doi.org/10.1093/ietisy/e90-1.1.334 db/journals/ieicet/ieicet90d.html#KumakiKIKMNDAS07

Kazutami Arimoto Toshihiro Hattori Hidehiro Takata Atsushi Hasegawa Toru Shimizu Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. 657-665 2007 90-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e90-c.4.657 db/journals/ieicet/ieicet90c.html#ArimotoHTHS07

Fukashi Morishita Hideyuki Noda Isamu Hayashi Takayuki Gyohten Mako Okamoto Takashi Ipposhi Shigeto Maegawa Katsumi Dosaka Kazutami Arimoto A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. 765-771 2007 90-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e90-c.4.765 db/journals/ieicet/ieicet90c.html#MorishitaNHGOIMDA07

Takeshi Kumaki Masakatsu Ishizaki Tetsushi Koide Hans Jürgen Mattausch Yasuto Kuroda Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Kazunori Saito Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. 1312-1315 2007 90-D IEICE Trans. Inf. Syst. 8 https://doi.org/10.1093/ietisy/e90-d.8.1312 db/journals/ieicet/ieicet90d.html#KumakiIKMKNDAS07

Hiroki Shimano Fukashi Morishita Katsumi Dosaka Kazutami Arimoto A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. 1927-1935 2007 90-C IEICE Trans. Electron. 10 https://doi.org/10.1093/ietele/e90-c.10.1927 db/journals/ieicet/ieicet90c.html#ShimanoMDA07

Hideyuki Noda Masami Nakajima Katsumi Dosaka Kiyoshi Nakata Motoki Higashida Osamu Yamamoto Katsuya Mizumoto Tetsushi Tanizaki Takayuki Gyohten Yoshihiro Okuno Hiroyuki Kondo Yukihiko Shimazu Kazutami Arimoto Kazunori Saito Toru Shimizu The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. 183-192 2007 42 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2006.886545 db/journals/jssc/jssc42.html#NodaNDNHYMTGOKS07

Hideyuki Noda Tetsushi Tanizaki Takayuki Gyohten Katsumi Dosaka Masami Nakajima Katsuya Mizumoto Kanako Yoshida Takenobu Iwao Tetsu Nishijima Yoshihiro Okuno Kazutami Arimoto The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. 804-812 2007 42 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2007.891680 db/journals/jssc/jssc42.html#NodaTGDNMYINOA07

Fukashi Morishita Isamu Hayashi Takayuki Gyohten Hideyuki Noda Takashi Ipposhi Hiroki Shimano Katsumi Dosaka Kazutami Arimoto A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. 853-861 2007 42 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2007.891677 db/journals/jssc/jssc42.html#MorishitaHGNISD07

Kazutami Arimoto Fukashi Morishita Isamu Hayashi Katsumi Dosaka Hiroki Shimano Takashi Ipposhi A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. 2611-2619 2007 42 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2007.907185 db/journals/jssc/jssc42.html#ArimotoMHDSI07

Takeshi Kumaki Tetsushi Koide Hans Jürgen Mattausch Yasuto Kuroda Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Kazunori Saito Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. 525-528 2007 conf/iscas/2007 ISCAS https://doi.org/10.1109/ISCAS.2007.378686 db/conf/iscas/iscas2007.html#KumakiKMKNDAS07 Hirokatsu Shirahama Akira Mochizuki Takahiro Hanyu Masami Nakajima Kazutami Arimoto Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. 43 2007 ISMVL https://doi.org/10.1109/ISMVL.2007.14 https://doi.ieeecomputersociety.org/10.1109/ISMVL.2007.14 conf/ismvl/2007 db/conf/ismvl/ismvl2007.html#ShirahamaMHNA07 Masaru Haraguchi Tokuya Osawa Akira Yamazaki Chikayoshi Morishima Toshinori Morihara Yoshikazu Morooka Yoshihiro Okuno Kazutami Arimoto A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. 490-491 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373508 conf/isscc/2007 db/conf/isscc/isscc2007.html#HaraguchiOYMMMOA07

Takayuki Gyohten Fukashi Morishita Isamu Hayashi Mako Okamoto Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Yasutaka Horiba An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. 1519-1525 2006 89-C IEICE Trans. Electron. 11 https://doi.org/10.1093/ietele/e89-c.11.1519 db/journals/ieicet/ieicet89c.html#GyohtenMHONDAH06

Hideyuki Noda Katsumi Dosaka Hans Jürgen Mattausch Tetsushi Koide Fukashi Morishita Kazutami Arimoto A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. 1612-1619 2006 89-C IEICE Trans. Electron. 11 https://doi.org/10.1093/ietele/e89-c.11.1612 db/journals/ieicet/ieicet89c.html#NodaDMKMA06

Kazutami Arimoto Fukashi Morishita Isamu Hayashi Tetsushi Tanizaki Takashi Ipposhi Katsumi Dosaka A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. 429-432 2006 CICC https://doi.org/10.1109/CICC.2006.321008 conf/cicc/2006 db/conf/cicc/cicc2006.html#ArimotoMHTID06 Masami Nakajima Hideyuki Noda Katsumi Dosaka Kiyoshi Nakata Motoki Higashida Osamu Yamamoto Katsuya Mizumoto Hiroyuki Kondo Yukihiko Shimazu Kazutami Arimoto Kazunori Saitoh Toru Shimizu A 40GOPS 250mW massively parallel processor based on matrix architecture. 1616-1625 2006 ISSCC https://doi.org/10.1109/ISSCC.2006.1696216 conf/isscc/2006 db/conf/isscc/isscc2006.html#NakajimaNDNHYMK06

Hideyuki Noda Kazunari Inoue Hans Jürgen Mattausch Tetsushi Koide Katsumi Dosaka Kazutami Arimoto Kazuyasu Fujishima Kenji Anami Tsutomu Yoshihara Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. 622-629 2005 88-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e88-c.4.622 db/journals/ieicet/ieicet88c.html#NodaIMKDAFAY05

Kazunari Inoue Hideyuki Noda Kazutami Arimoto Hans Jürgen Mattausch Tetsushi Koide A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. 1332-1342 2005 88-C IEICE Trans. Electron. 6 https://doi.org/10.1093/ietele/e88-c.6.1332 db/journals/ieicet/ieicet88c.html#InoueNAMK05

Akira Yamazaki Fukashi Morishita Naoya Watanabe Teruhiko Amano Masaru Haraguchi Hideyuki Noda Atsushi Hachisuka Katsumi Dosaka Kazutami Arimoto Setsuo Wake Hideyuki Ozaki Tsutomu Yoshihara A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. 2020-2027 2005 88-C IEICE Trans. Electron. 10 https://doi.org/10.1093/ietele/e88-c.10.2020 db/journals/ieicet/ieicet88c.html#YamazakiMWAHNHDAWOY05

Fukashi Morishita Isamu Hayashi Hideto Matsuoka Kazuhiro Takahashi Kuniyasu Shigeta Takayuki Gyohten Mitsutaka Niiro Hideyuki Noda Mako Okamoto Atsushi Hachisuka Atsushi Amo Hiroki Shinkawata Tatsuo Kasaoka Katsumi Dosaka Kazutami Arimoto Kazuyasu Fujishima Kenji Anami Tsutomu Yoshihara A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. 204-212 2005 40 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2004.837986 db/journals/jssc/jssc40.html#MorishitaHMTSGN05

Hideyuki Noda Kazunari Inoue Masayuki Kuroiwa Futoshi Igaue Kouji Yamamoto 0002 Hans Jürgen Mattausch Tetsushi Koide Atsushi Amo Atsushi Hachisuka Shinya Soeda Isamu Hayashi Fukashi Morishita Katsumi Dosaka Kazutami Arimoto Kazuyasu Fujishima Kenji Anami Tsutomu Yoshihara A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. 245-253 2005 40 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2004.838016 db/journals/jssc/jssc40.html#NodaIKIYMKAHSHM05

Masahisa Iida Naoki Kuroda Hidefumi Otsuka Masanobu Hirose Yuji Yamasaki Kiyoto Ohta Kazuhiko Shimakawa Takashi Nakabayashi Hiroyuki Yamauchi Tomohiko Sano Takayuki Gyohten Masanao Maruta Akira Yamazaki Fukashi Morishita Katsumi Dosaka Masahiko Takeuchi Kazutami Arimoto A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. 2296-2304 2005 40 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2005.857358 db/journals/jssc/jssc40.html#IidaKOHYOSNYSGM05

Fukashi Morishita Hideyuki Noda Takayuki Gyohten Mako Okamoto Takashi Ipposhi Shigeto Maegawa Katsumi Dosaka Kazutami Arimoto A capacitorless twin-transistor random access memory (TTRAM) on SOI. 435-438 2005 CICC https://doi.org/10.1109/CICC.2005.1568699 https://www.wikidata.org/entity/Q56112739 conf/cicc/2005 db/conf/cicc/cicc2005.html#MorishitaNGOIMD05 Hideyuki Noda Katsumi Dosaka Fukashi Morishita Kazutami Arimoto A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. 451-454 2005 CICC https://doi.org/10.1109/CICC.2005.1568703 conf/cicc/2005 db/conf/cicc/cicc2005.html#NodaDMA05 Takeshi Kumaki Yasuto Kuroda Tetsushi Koide Hans Jürgen Mattausch Hideyuki Noda Katsumi Dosaka Kazutami Arimoto Kazunori Saito CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. 5202-5205 2005 conf/iscas/2005 ISCAS (5) https://doi.org/10.1109/ISCAS.2005.1465807 db/conf/iscas/iscas2005-5.html#KumakiKKMNDAS05

Takeshi Fujino Akira Yamazaki Yasuhiko Taito Mitsuya Kinoshita Fukashi Morishita Teruhiko Amano Masaru Haraguchi Makoto Hatakenaka Atsushi Amo Atsushi Hachisuka Kazutami Arimoto Hideyuki Ozaki A Low Power Embedded DRAM Macro for Battery-Operated LSIs. 2991-3000 2003 86-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 http://search.ieice.org/bin/summary.php?id=e86-a_12_2991 db/journals/ieiceta/ieiceta86.html#FujinoYTKMAHHAH03

Yasuhiko Taito Tetsushi Tanizaki Mitsuya Kinoshita Futoshi Igaue Takeshi Fujino Kazutami Arimoto An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. 1967-1973 2003 38 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2003.818142 db/journals/jssc/jssc38.html#TaitoTKIFA03

Tadaaki Yamauchi Mitsuya Kinoshita Teruhiko Amano Katsumi Dosaka Kazutami Arimoto Hideyuki Ozaki Michihiro Yamada Tsutomu Yoshihara Design methodology of embedded DRAM with virtual-socket architecture. 46-54 2001 36 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/4.896228 db/journals/jssc/jssc36.html#YamauchiKADAOYY01

Yoshihiro Nagura Michael Mullins Anthony Sauvageau Yoshinoro Fujiwara Katsuya Furue Ryuji Ohmura Tatsunori Komoike Takenori Okitaka Tetsushi Tanizaki Katsumi Dosaka Kazutami Arimoto Yukiyoshi Koda Tetsuo Tada Test cost reduction by at-speed BISR for embedded DRAMs. 182-187 2001 conf/itc/2001 ITC db/conf/itc/itc2001.html#NaguraMSFFOKOTDAKT01 https://doi.org/10.1109/TEST.2001.966632 https://doi.ieeecomputersociety.org/10.1109/TEST.2001.966632

Tadaaki Yamauchi Fukashi Morishita Shigenobu Maeda Kazutami Arimoto Kazuyasu Fujishima Hideyuki Ozaki Tsutomu Yoshihara High-performance embedded SOI DRAM architecture for the low-power supply. 1169-1178 2000 35 IEEE J. Solid State Circuits 8 https://doi.org/10.1109/4.859506 db/journals/jssc/jssc35.html#YamauchiMMAFOY00

Akira Yamazaki Tadato Yamagata Makoto Hatakenaka Atsushi Miyanishi Isao Hayashi Shigeki Tomishima Atsuo Mangyo Yoshio Yukinari Takashi Tatsumi Masashi Matsumura Kazutami Arimoto Michihiro Yamada A 5.3-GB/s embedded SDRAM core with slight-boost scheme. 661-669 1999 34 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.760377 db/journals/jssc/jssc34.html#YamazakiYHMHTMY99

Takeshi Hamamoto Masaki Tsukude Kazutami Arimoto Yasuhiro Konishi Takayuki Miyamoto Hideyuki Ozaki Michihiro Yamada 400-MHz random column operating SDRAM techniques with self-skew compensation. 770-778 1998 33 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.668992 db/journals/jssc/jssc33.html#HamamotoTAKMOY98

Takahiro Tsuruda Mako Kobayashi Masaki Tsukude Tadato Yamagata Kazutami Arimoto Michihiro Yamada High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. 477-482 1997 32 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/4.557653 db/journals/jssc/jssc32.html#TsurudaKTYAY97

Ken'ichi Shimomura Hiroki Shimano Narumi Sakashita Fumihiro Okuda Toshiyuki Oashi Yasuo Yamaguchi Takahisa Eimori Masahide Inuishi Kazutami Arimoto Shigeto Maegawa Yasuo Inoue Shinji Komori Kazuo Kyuma A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. 1712-1720 1997 32 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.641691 db/journals/jssc/jssc32.html#ShimomuraSSOOYE97

Masaki Tsukude Shigehiro Kuge Takeshi Fujino Kazutami Arimoto A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. 1721-1727 1997 32 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.641692 db/journals/jssc/jssc32.html#TsukudeKFA97

Shigehiro Kuge Fukashi Morishita Takahiro Tsuruda Shigeki Tomishima Masaki Tsukude Tadato Yamagata Kazutami Arimoto SOI-DRAM circuit technologies for low power high speed multigiga scale memories. 586-591 1996 31 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.499736 db/journals/jssc/jssc31.html#KugeMTTTYA96

Narumi Sakashita Yasuhiko Nitta Ken'ichi Shimomura Fumihiro Okuda Hiroki Shimano Satoshi Yamakawa Masaki Tsukude Kazutami Arimoto Shinji Baba Shinji Komori Kazuo Kyuma Akihiko Yasuoka Haruhiko Abe A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. 1645-1655 1996 31 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.1996.542309 db/journals/jssc/jssc31.html#SakashitaNSOSYT96

Tadato Yamagata Shigeki Tomishima Masaki Tsukude Takahiro Tsuruda Yasushi Hashizume Kazutami Arimoto Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. 1183-1188 1995 November 30 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.475705 db/journals/jssc/jssc30.html#YamagataTTTHA95

Tsukasa Ooishi Mikio Asakura Shigeki Tomishima Hideto Hidaka Kazutami Arimoto Kazuyasu Fujishima A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. 432-440 1994 April 29 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.280692 db/journals/jssc/jssc29.html#OoishiATHAF94

Masaki Tsukude Kazutami Arimoto Hideto Hidaka Yasuhiro Konishi Masanori Hayashikoshi Katsuhiro Suma Kazuyasu Fujishima Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. 6-12 1993 10 IEEE Des. Test Comput. 2 https://doi.org/10.1109/54.211523 http://doi.ieeecomputersociety.org/10.1109/54.211523 db/journals/dt/dt10.html#TsukudeAHKHSF93

Masanori Hayashikoshi Hideto Hidaka Kazutami Arimoto Kazuyasu Fujishima A dual-mode sensing scheme of capacitor-coupled EEPROM cell. 569-573 1992 April 27 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.126545 db/journals/jssc/jssc27.html#HayashikoshiHAF92 streams/journals/jssc

Mikio Asakura Kazutami Arimoto Hideto Hidaka Kazuyasu Fujishima Cell-plate line connecting complementary bit-line (C<sup>3</sup>) architecture for battery-operated DRAMs. 597-602 1992 April 27 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.126549 db/journals/jssc/jssc27.html#AsakuraAHF92 streams/journals/jssc

Hideto Hidaka Kazutami Arimoto Kazuyasu Fujishima A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. 610-617 1992 April 27 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.126551 db/journals/jssc/jssc27.html#HidakaAF92 streams/journals/jssc

Hideto Hidaka Kazutami Arimoto Kazutoshi Hirayama Masanori Hayashikoshi Mikio Asakura Masaki Tsukude Tsukasa Oishi Shinji Kawai Katsuhiro Suma Yasuhiro Konishi Koji Tanaka Wataru Wakamiya Yoshikazu Ohno Kazuyasu Fujishima A 34-ns 16-Mb DRAM with controllable voltage down-converter. 1020-1027 1992 July 27 IEEE J. Solid State Circuits 7 https://doi.org/10.1109/4.142597 db/journals/jssc/jssc27.html#HidakaAHHATOKSKTWOF92 streams/journals/jssc

Masaki Tsukude Kazutami Arimoto Hideto Hidaka Yasuhiro Konishi Masanori Hayashikoshi Katsunori Suma Kazuyasu Fujishima A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. 615-622 1992 conf/itc/1992 ITC db/conf/itc/itc1992.html#TsukudeAHKHSF92 https://doi.org/10.1109/TEST.1992.527882 https://doi.ieeecomputersociety.org/10.1109/TEST.1992.527882

Kazutami Arimoto Mikio Asakura Hideto Hidaka Yoshio Matsuda Kazuyasu Fujishima A circuit design of intelligent cache DRAM with automatic write-back capability. 560-565 1991 April 26 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/4.75055 db/journals/jssc/jssc26.html#ArimotoAHMF91 streams/journals/jssc

Kazutami Arimoto Yoshio Matsuda Kiyohiro Furutani Masaki Tsukude Tsukasa Ooishi Koichiro Mashiko Kuzuyasu Fujishima A speed-enhanced DRAM array architecture with embedded ECC. 11-17 1990 February 25 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/4.50277 db/journals/jssc/jssc25.html#ArimotoMFTOMF90 streams/journals/jssc

Kiyohiro Furutani Kazutami Arimoto Hiroshi Miyamoto Toshifumi Kobayashi Kenichi Yasuda Koichiro Mashiko A built-in Hamming code ECC circuit for DRAMs. 50-56 1989 February 24 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/4.16301 db/journals/jssc/jssc24.html#FurutaniAMKYM89 streams/journals/jssc

Kazutami Arimoto Kazuyasu Fujishima Yoshio Matsuda Masaki Tsukude Tukasa Oishi Wataru Wakamiya Shin'ichi Satoh 0004 Michihiro Yamada Takao Nakano A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. 1184-1190 1989 October 24 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.1989.572576 db/journals/jssc/jssc24.html#ArimotoFMTOWSYN89 streams/journals/jssc

Yoshio Matsuda Kazutami Arimoto Masaki Tsukude Tsukasa Oishi Kazuyasu Fujishima A New Array Architecture for Parallel Testing in VLSI Memories. 322-326 1989 conf/itc/1989 ITC db/conf/itc/itc1989.html#MatsudaATOF89 https://doi.org/10.1109/TEST.1989.82315 https://doi.ieeecomputersociety.org/10.1109/TEST.1989.82315 Hiroshi Miyamoto Koichiro Mashiko Yoshikazu Morooka Kazutami Arimoto Michihiro Yamada Takao Nakano Test Pattern Considerations for Fault Tolerant High Density DRAM. 451-455 1985 conf/itc/1985 ITC db/conf/itc/itc1985.html#MiyamotoMMAYN85 Haruhiko Abe Hirohisa Aman Teruhiko Amano Sousuke Amasaki Atsushi Amo Kenji Anami Katsushi Asahina Mikio Asakura Shinji Baba Taisuke Boku Gangadhar Burra Katsumi Dosaka Takahisa Eimori Satoshi Fujii Takeshi Fujino Kazuyasu Fujishima Kuzuyasu Fujishima Hayato Fujiwara Hidehiro Fujiwara Yoshinoro Fujiwara Fumitaka Fukuzawa Katsuya Furue Kiyohiro Furutani Takayuki Gyohten Atsushi Hachisuka Christoph Hagleitner Takeshi Hamamoto Toshihiro Hanawa Takahiro Hanyu Masaru Haraguchi Pieter Harpe Atsushi Hasegawa Yasushi Hashizume Makoto Hatakenaka Toshihiro Hattori Yasushi Hayakawa Atsushi Hayami Isamu Hayashi Isao Hayashi Masanori Hayashikoshi Hideto Hidaka Motoki Higashida Takashi Higuchi Kazutoshi Hirayama Masanobu Hirose Masaki Hokari Yasutaka Horiba Futoshi Igaue Nao Igawa Masahisa Iida Atsuyuki Ikeya Yuta Imai Satoshi Imasu Kazuhiro Inaoka Kazunari Inoue Yasuo Inoue Masahide Inuishi Takashi Ipposhi Kazuya Ishida Kazuya Ishihara Masatoshi Ishikawa Koichi Ishimi Masakatsu Ishizaki Teruyuki Itoh Hisashi Iwamoto Takenobu Iwao Shunsuke Kamijo Satoshi Kaneko Tatsuo Kasaoka Sam Kavusi Hiroyuki Kawai Shinji Kawai Yoshifumi Kawamura Isao Kayano Kensaku Kinoshita Mitsuya Kinoshita Nobuhiro Kinoshita Masaya Kitao Mako Kobayashi Tomoki Kobayashi Toshifumi Kobayashi Yukiyoshi Koda Tetsushi Koide Tatsunori Komoike Kiyotaka Komoku Shinji Komori Takashi Komuro Hiroyuki Kondo Masafumi Kondo Yasuhiro Konishi Tomoya Kubo Shigehiro Kuge Takeshi Kumaki Takashi Kurafuji Naoki Kuroda Yasuto Kuroda Masayuki Kuroiwa Kazuo Kyuma Pattara Leelaprute Shigenobu Maeda Shigeto Maegawa Hiroshi Makino Atsuo Mangyo Masanao Maruta Koichiro Mashiko Norio Masui Yoshio Matsuda Akira Matsumoto Masashi Matsumura Tetsuya Matsumura Hideto Matsuoka Hans Jürgen Mattausch Shin'ichi Miura Kei Miyagi Hiroshi Miyamoto Takayuki Miyamoto Atsushi Miyanishi Hiroshi Miyata Hisashi Miyazaki Katsuya Mizumoto Hisayoshi Mizuno Akira Mochizuki Yushi Moko Tatsuya Mori Toshinori Morihara Chikayoshi Morishima Fukashi Morishita Yoshikazu Morooka Michael Mullins Kan Murata Yoshihiro Nagura Hayato Naito Takashi Nakabayashi Issei Nakaema Masami Nakajima Hirofumi Nakano Takao Nakano Kiyoshi Nakata Takashi Nasu Koji Nii Mitsutaka Niiro Yoshihiro Nishida Osamu Nishii Tetsu Nishijima Yasuhiko Nitta Hideyuki Noda Itaru Nonomura Toshiyuki Oashi Ryuji Ohmura Yoshikazu Ohno Kiyoto Ohta Tsukasa Oishi Tukasa Oishi Naoya Okada Daichi Okamoto Mako Okamoto Leona Okamura Keisuke Okazaki Takenori Okitaka Fumihiro Okuda Naoto Okumura Yoshihiro Okuno Shunsuke Okura Tsukasa Ooishi Tokuya Osawa Takeshi Oshita Yusuke Ota Sugako Otani Brian P. OtisBrian Otis Hidefumi Otsuka Hideyuki Ozaki Salilthip Phuklang Woogeun Rhee David Ruffieux Kazunori Saito Yoshihiro Saito Kazunori Saitoh Masatoshi Saitoh Narumi Sakashita Mamoru Sakugawa John Kenneth Salisbury Jr.Kenneth Salisbury Tomohiko Sano Masayuki Sato Mitsuhisa Sato Yoichiro Sato Shin'ichi Satoh 0004 Anthony Sauvageau Yoshihiro Sejima Satoshi Shigematsu Kuniyasu Shigeta Kazuhiko Shimakawa Hiroki Shimano Yukihiko Shimazu Toru Shimizu Eisuke Shimomura Ken'ichi Shimomura Hiroki Shinkawata Hirokatsu Shirahama Akio Shiratori Shinya Soeda Takeaki Sugimura Kimihoro Sugino Katsuhiro Suma Katsunori Suma Tetsuo Tada Yasuhiko Taito Kazuhiro Takahashi Mami Takahashi Hidekuni Takao Hidehiro Takata Hirokazu Takata Yukari Takata Masahiko Takeuchi Koji Tanaka Ryugo Tanaka Shouichiro Tanifuji Tetsushi Tanizaki Takashi Tatsumi Shigeki Tomishima Kazuma Toyota Masaki Tsukude Takahiro Tsuruda Kazuhiro Ueda Minoru Uemura Wataru Wakamiya Setsuo Wake Naoya Watanabe Yoshihiro Watanabe Kazuki Watatani Kazuki Wayama Makoto Yabuuchi Michihiro Yamada Tadato Yamagata Yasuo Yamaguchi Satoshi Yamakawa Koji Yamamoto 0002Kouji Yamamoto 0002 Osamu Yamamoto Hiroyuki Yamasaki Yuji Yamasaki Daichi Yamashita Hiroyuki Yamauchi Hitoshi Yamauchi Tadaaki Yamauchi Akira Yamazaki Yuji Yano Kenichi Yasuda Akihiko Yasuoka Tomoyuki Yokogawa Kanako Yoshida Tsutomu Yoshihara Noriaki Yoshikawa Takuma Yoshimura Yoshio Yukinari