Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.

Hiromitsu Imori Hiroshi Nakamura Kisaburo Nakazawa Hang Li Hiromitsu Imori Taisuke Boku Ikuo Nakata Yoshiyuki Yamashita Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. 368-377 1994 conf/hicss/1994 HICSS (1) db/conf/hicss/hicss1994.html#NakamuraNLIBNY94 https://doi.org/10.1109/HICSS.1994.323156 Hiroshi Nakamura Taisuke Boku Hideo Wada Hiromitsu Imori Ikuo Nakata Yasuhiro Inagami Kisaburo Nakazawa Yoshiyuki Yamashita A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. 298-307 1993 conf/ics/1993 International Conference on Supercomputing https://doi.org/10.1145/165939.165998 https://www.wikidata.org/entity/Q130994177 db/conf/ics/ics1993.html#NakamuraBWININY93 Kisaburo Nakazawa Hiroshi Nakamura Hiromitsu Imori Shun Kawabe Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. 642-651 1992 conf/sc/1992 SC db/conf/sc/sc1992.html#NakazawaNIK92 https://doi.org/10.1109/SUPERC.1992.236638 https://doi.ieeecomputersociety.org/10.1109/SUPERC.1992.236638 http://dl.acm.org/citation.cfm?id=148106 Taisuke Boku Yasuhiro Inagami Shun Kawabe Hang Li Hiroshi Nakamura Ikuo Nakata Kisaburo Nakazawa Hideo Wada Yoshiyuki Yamashita