Coulomb blockade in PtSi/porous Si Schottky barrier as a two-dimensional multi-tunnelling junction.

Farshid Raissi

Abbas Erfanian Hamed Mehrara Farshid Raissi Mahdi Khaje Coulomb blockade in PtSi/porous Si Schottky barrier as a two-dimensional multi-tunnelling junction. 81-86 2015 9 IET Circuits Devices Syst. 2 https://doi.org/10.1049/iet-cds.2013.0475 db/journals/iet-cds/iet-cds9.html#ErfanianMRK15

Ghader Yosefi Sattar Mirzakuchaki Farshid Raissi Saeid Afrang Design and Analysis of a High Force, Low Voltage and High Flow Rate Electro-Thermal Micropump. 1323-1341 2014 5 Micromachines 4 https://doi.org/10.3390/mi5041323 db/journals/micromachines/micromachines5.html#YosefiMRA14

Ahmad Afifi Ahmad Ayatollahi Farshid Raissi CMOL implementation of spiking neurons and spike-timing dependent plasticity. 357-372 2011 39 Int. J. Circuit Theory Appl. 4 https://doi.org/10.1002/cta.638 db/journals/ijcta/ijcta39.html#AfifiAR11

Farzan Jazayeri Farshid Raissi Behjat Forouzandeh Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET. 371-376 2010 7 IEICE Electron. Express 5 https://doi.org/10.1587/elex.7.371 db/journals/ieiceee/ieiceee7.html#JazayeriRF10

Farzan Jazayeri Ahmad Sammak Behjat Forouzandeh Farshid Raissi A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode. 906-912 2010 7 IEICE Electron. Express 13 https://doi.org/10.1587/elex.7.906 db/journals/ieiceee/ieiceee7.html#JazayeriSFR10

Ahmad Afifi Ahmad Ayatollahi Farshid Raissi Hassan Hajghassem Efficient Hybrid CMOS-Nano Circuit Design for Spiking Neurons and Memristive Synapses with STDP. 1670-1677 2010 93-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 9 https://doi.org/10.1587/transfun.E93.A.1670 http://search.ieice.org/bin/summary.php?id=e93-a_9_1670 db/journals/ieicet/ieicet93a.html#AfifiARH10

Farzan Jazayeri Behjat Forouzandeh Farshid Raissi Low-power variable gain amplifier with wide UGBW based on nanoscale Field Effect Diode. 51-57 2009 6 IEICE Electron. Express 1 https://doi.org/10.1587/elex.6.51 db/journals/ieiceee/ieiceee6.html#JazayeriFR09

Ahmad Afifi Ahmad Ayatollahi Farshid Raissi STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks. 148-153 2009 6 IEICE Electron. Express 3 https://doi.org/10.1587/elex.6.148 db/journals/ieiceee/ieiceee6.html#AfifiAR09

Mina Amirmazlaghani Farshid Raissi Memory cell using Modified Field Effect Diode. 1582-1586 2009 6 IEICE Electron. Express 22 https://doi.org/10.1587/elex.6.1582 db/journals/ieiceee/ieiceee6.html#AmirmazlaghaniR09

Ahmad Afifi Ahmad Ayatollahi Farshid Raissi Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits. 563-566 2009 ECCTD https://doi.org/10.1109/ECCTD.2009.5275035 conf/ecctd/2009 db/conf/ecctd/ecctd2009.html#AfifiAR09

Ali Mirvakili Mohammad Yavari Farshid Raissi A linear current-reused LNA for 3.1-10.6GHz UWB receivers. 908-914 2008 5 IEICE Electron. Express 21 https://doi.org/10.1587/elex.5.908 db/journals/ieiceee/ieiceee5.html#MirvakiliYR08

Majid Jalalifar Mohammad Yavari Farshid Raissi A novel topology in RNMC amplifiers with single miller compensation capacitor. 296-299 2008 ISCAS https://doi.org/10.1109/ISCAS.2008.4541413 conf/iscas/2008 db/conf/iscas/iscas2008.html#JalalifarYR08 Majid Jalalifar Mohammad Yavari Farshid Raissi A novel topology in reversed nested miller compensation using dual-active capacitance. 2270-2273 2008 ISCAS https://doi.org/10.1109/ISCAS.2008.4541906 conf/iscas/2008 db/conf/iscas/iscas2008.html#JalalifarYR08a Massoud Masoumi Farshid Raissi Mahmoud Ahmadian NanoCMOS-Molecular Realization of Rijndael. 285-297 2006 conf/ches/2006 CHES https://doi.org/10.1007/11894063_23 db/conf/ches/ches2006.html#MasoumiRA06

Iraj Sheikhian Farshid Raissi An Improved Differential Comparator with Field Effect Diode Output Stage. 931-938 2005 14 J. Circuits Syst. Comput. 5 https://doi.org/10.1142/S0218126605002684 db/journals/jcsc/jcsc14.html#SheikhianR05

Nasser Masoumi Mahmoud Ahmadian Farshid Raissi Massoud Masoumi Jahan B. Ghasemi Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. 283-288 2005 conf/iwsoc/2005 IWSOC https://doi.org/10.1109/IWSOC.2005.57 https://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.57 db/conf/iwsoc/iwsoc2005.html#MasoumiARMG05 Ahmad Afifi Saeid Afrang Mahmoud Ahmadian Mina Amirmazlaghani Ahmad Ayatollahi Abbas Erfanian Behjat Forouzandeh Jahan B. Ghasemi Hassan Hajghassem Majid Jalalifar Farzan Jazayeri Mahdi Khaje Massoud Masoumi Nasser Masoumi Hamed Mehrara Ali Mirvakili Sattar Mirzakuchaki Ahmad Sammak Iraj Sheikhian Mohammad Yavari Ghader Yosefi