<?xml version="1.0"?>
<dblpperson name="Ilya Ganusov" pid="80/4703" n="14">
<person key="homepages/80/4703" mdate="2020-10-20">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="80/4703">Ilya K. Ganusov</author>
</person>
<r><inproceedings key="conf/fpl/ZgheibLG21" mdate="2021-10-18">
<author pid="33/9240">Grace Zgheib</author>
<author pid="303/8840">Yu Shen Lu</author>
<author pid="80/4703">Ilya Ganusov</author>
<title>Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming.</title>
<pages>327-333</pages>
<year>2021</year>
<booktitle>FPL</booktitle>
<ee>https://doi.org/10.1109/FPL53798.2021.00064</ee>
<crossref>conf/fpl/2021</crossref>
<url>db/conf/fpl/fpl2021.html#ZgheibLG21</url>
</inproceedings>
</r>
<r><inproceedings key="conf/fpga/ChromczakWCHLVZ20" mdate="2025-01-19">
<author pid="71/7863">Jeffrey Chromczak</author>
<author pid="259/3966">Mark Wheeler</author>
<author pid="136/3821">Charles Chiasson</author>
<author orcid="0000-0003-2843-1972" pid="175/6204">Dana How</author>
<author pid="86/4036">Martin Langhammer</author>
<author pid="69/4160">Tim Vanderhoek</author>
<author pid="33/9240">Grace Zgheib</author>
<author pid="80/4703">Ilya Ganusov</author>
<title>Architectural Enhancements in Intel&#174; Agilex&#8482; FPGAs.</title>
<pages>140-149</pages>
<year>2020</year>
<booktitle>FPGA</booktitle>
<ee>https://doi.org/10.1145/3373087.3375308</ee>
<ee>https://www.wikidata.org/entity/Q130844474</ee>
<crossref>conf/fpga/2020</crossref>
<url>db/conf/fpga/fpga2020.html#ChromczakWCHLVZ20</url>
</inproceedings>
</r>
<r><inproceedings key="conf/hotchips/GanusovICM20" mdate="2021-10-14">
<author pid="80/4703">Ilya K. Ganusov</author>
<author orcid="0000-0002-1045-0019" pid="71/2489">Mahesh A. Iyer</author>
<author pid="86/797">Ning Cheng</author>
<author pid="246/0730">Alon Meisler</author>
<title>Agilex&#8482; Generation of Intel&#174; FPGAs.</title>
<pages>1-26</pages>
<year>2020</year>
<booktitle>Hot Chips Symposium</booktitle>
<ee>https://doi.org/10.1109/HCS49909.2020.9220557</ee>
<crossref>conf/hotchips/2020</crossref>
<url>db/conf/hotchips/hotchips2020.html#GanusovICM20</url>
</inproceedings>
</r>
<r><article key="journals/micro/AhmadBGKRW16" mdate="2025-03-03">
<author orcid="0000-0001-7059-544X" pid="179/0644">Sagheer Ahmad</author>
<author pid="17/3078">Vamsi Boppana</author>
<author pid="80/4703">Ilya Ganusov</author>
<author pid="31/1947">Vinod Kathail</author>
<author pid="59/2817">Vidya Rajagopalan</author>
<author pid="57/4914">Ralph Wittig</author>
<title>A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform.</title>
<pages>48-62</pages>
<year>2016</year>
<volume>36</volume>
<journal>IEEE Micro</journal>
<number>2</number>
<ee>https://doi.org/10.1109/MM.2016.18</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MM.2016.18</ee>
<url>db/journals/micro/micro36.html#AhmadBGKRW16</url>
</article>
</r>
<r><inproceedings key="conf/fpl/GanusovD16" mdate="2017-05-21">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="186/8736">Benjamin Devlin</author>
<title>Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs.</title>
<pages>1-9</pages>
<year>2016</year>
<booktitle>FPL</booktitle>
<ee>https://doi.org/10.1109/FPL.2016.7577343</ee>
<crossref>conf/fpl/2016</crossref>
<url>db/conf/fpl/fpl2016.html#GanusovD16</url>
</inproceedings>
</r>
<r><inproceedings key="conf/fpl/GanusovFNPD16" mdate="2017-05-21">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="33/5604">Henri Fraisse</author>
<author pid="186/8732">Aaron Ng</author>
<author pid="57/10596">Rafael Trapani Possignolo</author>
<author pid="177/9408">Sabya Das</author>
<title>Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.</title>
<pages>1-10</pages>
<year>2016</year>
<booktitle>FPL</booktitle>
<ee>https://doi.org/10.1109/FPL.2016.7577344</ee>
<crossref>conf/fpl/2016</crossref>
<url>db/conf/fpl/fpl2016.html#GanusovFNPD16</url>
</inproceedings>
</r>
<r><inproceedings key="conf/hotchips/BoppanaAGKRW15" mdate="2025-04-01">
<author pid="17/3078">Vamsi Boppana</author>
<author orcid="0000-0001-7059-544X" pid="179/0644">Sagheer Ahmad</author>
<author pid="80/4703">Ilya Ganusov</author>
<author pid="31/1947">Vinod Kathail</author>
<author pid="59/2817">Vidya Rajagopalan</author>
<author pid="57/4914">Ralph Wittig</author>
<title>UltraScale+ MPSoC and FPGA families.</title>
<pages>1-37</pages>
<year>2015</year>
<booktitle>Hot Chips Symposium</booktitle>
<ee>https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477457</ee>
<crossref>conf/hotchips/2015</crossref>
<url>db/conf/hotchips/hotchips2015.html#BoppanaAGKRW15</url>
</inproceedings>
</r>
<r><article key="journals/taco/GanusovB06" mdate="2021-02-17">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="93/903">Martin Burtscher</author>
<title>Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.</title>
<pages>424-449</pages>
<year>2006</year>
<volume>3</volume>
<journal>ACM Trans. Archit. Code Optim.</journal>
<number>4</number>
<ee type="oa">https://doi.org/10.1145/1187976.1187979</ee>
<url>db/journals/taco/taco3.html#GanusovB06</url>
</article>
</r>
<r><inproceedings key="conf/IEEEpact/GanusovB06" mdate="2021-08-11">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="93/903">Martin Burtscher</author>
<title>Efficient emulation of hardware prefetchers via event-driven helper threading.</title>
<pages>144-153</pages>
<year>2006</year>
<crossref>conf/IEEEpact/2006</crossref>
<booktitle>PACT</booktitle>
<ee>https://doi.org/10.1145/1152154.1152178</ee>
<ee>https://ieeexplore.ieee.org/document/7847590/</ee>
<url>db/conf/IEEEpact/pact2006.html#GanusovB06</url>
</inproceedings>
</r>
<r><article key="journals/dt/LiuGBT05" mdate="2020-05-17">
<author pid="10/4856">Christianto C. Liu</author>
<author pid="80/4703">Ilya Ganusov</author>
<author pid="93/903">Martin Burtscher</author>
<author pid="73/2127">Sandip Tiwari</author>
<title>Bridging the Processor-Memory Performance Gapwith 3D IC Technology.</title>
<pages>556-564</pages>
<year>2005</year>
<volume>22</volume>
<journal>IEEE Des. Test Comput.</journal>
<number>6</number>
<ee>https://doi.org/10.1109/MDT.2005.134</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MDT.2005.134</ee>
<url>db/journals/dt/dt22.html#LiuGBT05</url>
</article>
</r>
<r><article key="journals/tc/BurtscherGJKRS05" mdate="2017-05-20">
<author pid="93/903">Martin Burtscher</author>
<author pid="80/4703">Ilya Ganusov</author>
<author pid="88/4500">Sandra J. Jackson</author>
<author pid="96/35">Jian Ke</author>
<author pid="44/3427">Paruj Ratanaworabhan</author>
<author pid="49/122">Nana B. Sam</author>
<title>The VPC Trace-Compression Algorithms.</title>
<pages>1329-1344</pages>
<year>2005</year>
<volume>54</volume>
<journal>IEEE Trans. Computers</journal>
<number>11</number>
<ee>https://doi.org/10.1109/TC.2005.186</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/TC.2005.186</ee>
<url>db/journals/tc/tc54.html#BurtscherGJKRS05</url>
</article>
</r>
<r><inproceedings key="conf/ACMmsp/GanusovB05" mdate="2018-11-06">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="93/903">Martin Burtscher</author>
<title>On the importance of optimizing the configuration of stream prefetchers.</title>
<pages>54-61</pages>
<year>2005</year>
<crossref>conf/ACMmsp/2005</crossref>
<booktitle>Memory System Performance</booktitle>
<ee>https://doi.org/10.1145/1111583.1111591</ee>
<url>db/conf/ACMmsp/msp2005.html#GanusovB05</url>
</inproceedings>
</r>
<r><inproceedings key="conf/IEEEpact/GanusovB05" mdate="2023-03-24">
<author pid="80/4703">Ilya Ganusov</author>
<author pid="93/903">Martin Burtscher</author>
<title>Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors.</title>
<pages>350-360</pages>
<year>2005</year>
<crossref>conf/IEEEpact/2005</crossref>
<booktitle>IEEE PACT</booktitle>
<ee>https://doi.org/10.1109/PACT.2005.23</ee>
<ee>https://doi.ieeecomputersociety.org/10.1109/PACT.2005.23</ee>
<url>db/conf/IEEEpact/IEEEpact2005.html#GanusovB05</url>
</inproceedings>
</r>
<r><inproceedings key="conf/micro/BurtscherG04" mdate="2025-01-19">
<author pid="93/903">Martin Burtscher</author>
<author pid="80/4703">Ilya Ganusov</author>
<title>Automatic Synthesis of High-Speed Processor Simulators.</title>
<pages>55-66</pages>
<year>2004</year>
<crossref>conf/micro/2004</crossref>
<booktitle>MICRO</booktitle>
<ee>https://doi.org/10.1109/MICRO.2004.7</ee>
<ee>https://doi.ieeecomputersociety.org/10.1109/MICRO.2004.7</ee>
<ee>http://dl.acm.org/citation.cfm?id=1038931</ee>
<ee>https://www.wikidata.org/entity/Q130991883</ee>
<url>db/conf/micro/micro2004.html#BurtscherG04</url>
</inproceedings>
</r>
<coauthors n="28" nc="4">
<co c="0"><na f="a/Ahmad:Sagheer" pid="179/0644">Sagheer Ahmad</na></co>
<co c="0"><na f="b/Boppana:Vamsi" pid="17/3078">Vamsi Boppana</na></co>
<co c="1"><na f="b/Burtscher:Martin" pid="93/903">Martin Burtscher</na></co>
<co c="3"><na f="c/Cheng:Ning" pid="86/797">Ning Cheng</na></co>
<co c="0"><na f="c/Chiasson:Charles" pid="136/3821">Charles Chiasson</na></co>
<co c="0"><na f="c/Chromczak:Jeffrey" pid="71/7863">Jeffrey Chromczak</na></co>
<co c="2"><na f="d/Das:Sabya" pid="177/9408">Sabya Das</na></co>
<co c="-1"><na f="d/Devlin:Benjamin" pid="186/8736">Benjamin Devlin</na></co>
<co c="2"><na f="f/Fraisse:Henri" pid="33/5604">Henri Fraisse</na></co>
<co c="0"><na f="h/How:Dana" pid="175/6204">Dana How</na></co>
<co c="3"><na f="i/Iyer:Mahesh_A=" pid="71/2489">Mahesh A. Iyer</na></co>
<co c="1"><na f="j/Jackson:Sandra_J=" pid="88/4500">Sandra J. Jackson</na></co>
<co c="0"><na f="k/Kathail:Vinod" pid="31/1947">Vinod Kathail</na></co>
<co c="1"><na f="k/Ke:Jian" pid="96/35">Jian Ke</na></co>
<co c="0"><na f="l/Langhammer:Martin" pid="86/4036">Martin Langhammer</na></co>
<co c="1"><na f="l/Liu:Christianto_C=" pid="10/4856">Christianto C. Liu</na></co>
<co c="0"><na f="l/Lu:Yu_Shen" pid="303/8840">Yu Shen Lu</na></co>
<co c="3"><na f="m/Meisler:Alon" pid="246/0730">Alon Meisler</na></co>
<co c="2"><na f="n/Ng:Aaron" pid="186/8732">Aaron Ng</na></co>
<co c="2"><na f="p/Possignolo:Rafael_Trapani" pid="57/10596">Rafael Trapani Possignolo</na></co>
<co c="0"><na f="r/Rajagopalan:Vidya" pid="59/2817">Vidya Rajagopalan</na></co>
<co c="1"><na f="r/Ratanaworabhan:Paruj" pid="44/3427">Paruj Ratanaworabhan</na></co>
<co c="1"><na f="s/Sam:Nana_B=" pid="49/122">Nana B. Sam</na></co>
<co c="1"><na f="t/Tiwari:Sandip" pid="73/2127">Sandip Tiwari</na></co>
<co c="0"><na f="v/Vanderhoek:Tim" pid="69/4160">Tim Vanderhoek</na></co>
<co c="0"><na f="w/Wheeler:Mark" pid="259/3966">Mark Wheeler</na></co>
<co c="0"><na f="w/Wittig:Ralph" pid="57/4914">Ralph Wittig</na></co>
<co c="0"><na f="z/Zgheib:Grace" pid="33/9240">Grace Zgheib</na></co>
</coauthors>
</dblpperson>

