Katsuhiko Shimabukuro
Keisuke Tokuhira
Morikazu Nakamura
Mitsunaga Kinjo
Katsuhiko Shimabukuro
QUBO Model Formulation Based on Petri Net Behavioral Description for Combinatorial Optimization Problems.
811-821
2022
ICO
https://doi.org/10.1007/978-3-031-19958-5_77
db/conf/ico/ico2022.html#TokuhiraNKS22
Katsuhiko Shimabukuro
Michitaka Kameyama
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic.
19-24
2017
ISMVL
https://doi.org/10.1109/ISMVL.2017.45
https://doi.ieeecomputersociety.org/10.1109/ISMVL.2017.45
conf/ismvl/2017
db/conf/ismvl/ismvl2017.html#ShimabukuroK17
Mitsunaga Kinjo
Katsuhiko Shimabukuro
Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution.
302-306
2011
ISMVL
https://doi.org/10.1109/ISMVL.2011.63
https://doi.ieeecomputersociety.org/10.1109/ISMVL.2011.63
conf/ismvl/2011
db/conf/ismvl/ismvl2011.html#KinjoS11
Takahiro Hanyu
Michitaka Kameyama
Katsuhiko Shimabukuro
Chotei Zukeran
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
167-172
2001
conf/ismvl/2001
ISMVL
db/conf/ismvl/ismvl2001.html#HanyuKSZ01
https://doi.org/10.1109/ISMVL.2001.924568
https://doi.ieeecomputersociety.org/10.1109/ISMVL.2001.924568
Katsuhiko Shimabukuro
Chotei Zukeran
Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits.
282-288
1998
conf/ismvl/1998
ISMVL
https://doi.org/10.1109/ISMVL.1998.679471
https://doi.ieeecomputersociety.org/10.1109/ISMVL.1998.679471
db/conf/ismvl/ismvl1998.html#ShimabukuroZ98
Katsuhiko Shimabukuro
Michitaka Kameyama
Tatsuo Higuchi 0001
Design of a Multiple-Valued VLSI Processor for Digital Control.
322-329
1992
conf/ismvl/1992
ISMVL
db/conf/ismvl/ismvl1992.html#ShimabukuroKH92
https://doi.org/10.1109/ISMVL.1992.186813
https://doi.ieeecomputersociety.org/10.1109/ISMVL.1992.186813
Takahiro Hanyu
Tatsuo Higuchi 0001
Michitaka Kameyama
Mitsunaga Kinjo
Morikazu Nakamura
Keisuke Tokuhira
Chotei Zukeran