An SRAM-Based PUF with High Native-Stability Using Alternative Configuration Technique.

Hsin-Shu Chen Sharon Isabelle Timotius Yi-Lun Wang Hsin-Shu Chen An SRAM-Based PUF with High Native-Stability Using Alternative Configuration Technique. 1-6 2025 ICCE https://doi.org/10.1109/ICCE63647.2025.10929913 conf/iccel/2025 db/conf/iccel/icce2025.html#TimotiusWC25 Chi-Wei Chen Jia-Yi Chen Hsin-Shu Chen A 94.8% Peak-Efficiency 3-Level Buck Converter with Fast Flying Capacitor Charging Technique. 1-4 2025 ISCAS https://doi.org/10.1109/ISCAS56072.2025.11043824 conf/iscas/2025 db/conf/iscas/iscas2025.html#ChenCC25

Shih-Bo Yu Chun-Hao Liang Chien-Ping Hung Yu-Lin Chen Pei-Kai Liao Jia-Han Li Hsin-Shu Chen Chia-Ray Chen Chien-Kai Tseng Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations. 1-12 2024 73 IEEE Trans. Instrum. Meas. https://doi.org/10.1109/TIM.2024.3480207 db/journals/tim/tim73.html#YuLHCLLCCT24 streams/journals/tim

Jun-Yi Wu Hsin-Shu Chen A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback. 375-379 2023 MWSCAS https://doi.org/10.1109/MWSCAS57524.2023.10405977 conf/mwscas/2023 db/conf/mwscas/mwscas2023.html#WuC23 Chi-Wei Chen Chien-Yu Su Hsin-Shu Chen A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC. 3483-3487 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937223 conf/iscas/2022 db/conf/iscas/iscas2022.html#ChenSC22 Tun-Yen Liao Hsin-Shu Chen Wen-Jong Wu Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques. 1-4 2021 ISCAS https://doi.org/10.1109/ISCAS51556.2021.9401096 conf/iscas/2021 db/conf/iscas/iscas2021.html#LiaoCW21 Hsin-Shu Chen Sheng-Hsiang Huang Hung-Yen Tai Sen-Wei Lin Shih-Wei Wu A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. 1-4 2020 ISCAS https://doi.org/10.1109/ISCAS45731.2020.9180538 conf/iscas/2020 db/conf/iscas/iscas2020.html#ChenHTLW20

Yao-Sheng Hu Li-Yu Huang Hsin-Shu Chen A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. 2680-2690 2019 54 IEEE J. Solid State Circuits 10 https://doi.org/10.1109/JSSC.2019.2921481 https://www.wikidata.org/entity/Q127612399 db/journals/jssc/jssc54.html#HuHC19

Chi-Wei Chen Hsin-Shu Chen Wen-Jong Wu A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique. 806-809 2019 MWSCAS https://doi.org/10.1109/MWSCAS.2019.8885078 conf/mwscas/2019 db/conf/mwscas/mwscas2019.html#ChenCW19 Yao-Sheng Hu Li-Yu Huang Hsin-Shu Chen A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. 103-106 2018 A-SSCC https://doi.org/10.1109/ASSCC.2018.8579298 conf/asscc/2018 db/conf/asscc/asscc2018.html#HuHC18 Yao-Sheng Hu Jhao-Huei Lin Ding-Guo Lin Kai-Yue Lin Hsin-Shu Chen An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. 253-256 2018 A-SSCC https://doi.org/10.1109/ASSCC.2018.8579310 conf/asscc/2018 db/conf/asscc/asscc2018.html#HuLLLC18 Kai-Ren Cheng Hsin-Shu Chen Mickaël Lallart Wen-Jong Wu A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. 1-4 2018 ISCAS https://doi.org/10.1109/ISCAS.2018.8351700 conf/iscas/2018 db/conf/iscas/iscas2018.html#ChengCLW18 Hsin-Shu Chen Jia-Nan Tai Yi-Jan Emery Chen Jau-Horng Chen A current average control method for transient-glitch reduction in variable frequency DC-DC converters. 1-4 2017 ISCAS https://doi.org/10.1109/ISCAS.2017.8050586 conf/iscas/2017 db/conf/iscas/iscas2017.html#ChenTCC17

Tsung-Han Tsai Hung-Yen Tai Pao-Yang Tsai Cheng-Hsueh Tsai Hsin-Shu Chen An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. 683-692 2016 63-I IEEE Trans. Circuits Syst. I Regul. Pap. 5 https://doi.org/10.1109/TCSI.2016.2529278 db/journals/tcas/tcasI63.html#TsaiTTTC16

Yao-Sheng Hu Po-Chao Huang Hung-Yen Tai Hsin-Shu Chen A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. 1166-1170 2016 63-II IEEE Trans. Circuits Syst. II Express Briefs 12 https://doi.org/10.1109/TCSII.2016.2608908 db/journals/tcas/tcasII63.html#HuHTC16

Yao-Sheng Hu Po-Chao Huang Mi-Ti Yang Shih-Wei Wu Hsin-Shu Chen A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC. 81-84 2016 A-SSCC https://doi.org/10.1109/ASSCC.2016.7844140 conf/asscc/2016 db/conf/asscc/asscc2016.html#HuHYWC16 Yao-Sheng Hu Kai-Yue Lin Hsin-Shu Chen A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique. 149-152 2016 A-SSCC https://doi.org/10.1109/ASSCC.2016.7844157 conf/asscc/2016 db/conf/asscc/asscc2016.html#HuLC16 Po-Chao Huang Yao-Sheng Hu Hung-Yen Tai Hsin-Shu Chen An 8-bit 900MS/S two-step SAR ADC. 2898 2016 ISCAS https://doi.org/10.1109/ISCAS.2016.7539201 conf/iscas/2016 db/conf/iscas/iscas2016.html#HuangHTC16

Hung-Yen Tai Cheng-Hsueh Tsai Pao-Yang Tsai Hung-Wei Chen Hsin-Shu Chen A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. 339-343 2014 61-II IEEE Trans. Circuits Syst. II Express Briefs 5 https://doi.org/10.1109/TCSII.2014.2312642 db/journals/tcas/tcasII61.html#TaiTTCC14

Chien-Jian Tseng Chieh-Fan Lai Hsin-Shu Chen A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. 2805-2815 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 10 https://doi.org/10.1109/TCSI.2014.2333672 db/journals/tcas/tcasI61.html#TsengLC14

Yao-Sheng Hu Chi-Huai Shih Hung-Yen Tai Hung-Wei Chen Hsin-Shu Chen A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. 81-84 2014 A-SSCC https://doi.org/10.1109/ASSCC.2014.7008865 conf/asscc/2014 db/conf/asscc/asscc2014.html#HuSTCC14 Hung-Yen Tai Yao-Sheng Hu Hung-Wei Chen Hsin-Shu Chen 11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. 196-197 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757397 conf/isscc/2014 db/conf/isscc/isscc2014.html#TaiHCC14

Chien-Jian Tseng Yi-Chun Hsieh Ching-Hua Yang Hsin-Shu Chen A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. 2902-2910 2013 60-I IEEE Trans. Circuits Syst. I Regul. Pap. 11 https://doi.org/10.1109/TCSI.2013.2256212 db/journals/tcas/tcasI60.html#TsengHYC13

Chien-Jian Tseng Hung-Wei Chen Wei-Ting Shen Wei-Chih Cheng Hsin-Shu Chen A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. 1334-1343 2012 47 IEEE J. Solid State Circuits 6 https://doi.org/10.1109/JSSC.2012.2192655 db/journals/jssc/jssc47.html#TsengCSCC12

Pang-Jung Liu Wei-Shan Ye Jia-Nan Tai Hsin-Shu Chen Jau-Horng Chen Yi-Jan Emery Chen A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time. 575-583 2012 59-I IEEE Trans. Circuits Syst. I Regul. Pap. 3 https://doi.org/10.1109/TCSI.2011.2167259 db/journals/tcas/tcasI59.html#LiuYTCCC12

Jia-Nan Tai Hsin-Shu Chen Hang-Quei Chiu A highly integrated class-D amplifier using driver delay hysteresis control. 1-4 2012 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2012.6212661 conf/vlsi-dat/2012 db/conf/vlsi-dat/vlsi-dat2012.html#TaiCC12 Hung-Yen Tai Hung-Wei Chen Hsin-Shu Chen A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. 92-93 2012 VLSIC https://doi.org/10.1109/VLSIC.2012.6243805 conf/vlsic/2012 db/conf/vlsic/vlsic2012.html#TaiCC12

Hsin-Shu Chen Jyun-Cheng Lin A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop. 855-860 2010 93-C IEICE Trans. Electron. 6 https://doi.org/10.1587/transele.E93.C.855 http://search.ieice.org/bin/summary.php?id=e93-c_6_855 db/journals/ieicet/ieicet93c.html#ChenL10

Hung-Wei Chen I-Ching Chen Huan-Chieh Tseng Hsin-Shu Chen A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS. 3051-3059 2009 44 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2009.2032258 db/journals/jssc/jssc44.html#ChenCTC09

Sen-Wen Hsiao Yen-Chih Huang David Liang Hung-Wei Kevin Chen Hsin-Shu Chen A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692648 db/conf/iscas/iscas2006.html#HsiaoHLCC06 Hsin-Shu Chen High-Resolution Nyquist -Rate Analog -to -Digital Converter University of Illinois Urbana-Champaign, USA 2001 https://hdl.handle.net/2142/80704

Hsin-Shu Chen Bang-Sup Song Kantilal Bacrania A 14-b 20-Msamples/s CMOS pipelined ADC. 997-1001 2001 36 IEEE J. Solid State Circuits 6 https://doi.org/10.1109/4.924862 db/journals/jssc/jssc36.html#ChenSB01

Hsin-Shu Chen A. Ito Characterization of 1/f noise vs. number of gate stripes in MOS transistors. 310-313 1999 conf/iscas/1999 ISCAS (2) https://doi.org/10.1109/ISCAS.1999.780720 db/conf/iscas/iscas1999-2.html#ChenI99 Kantilal Bacrania Chi-Wei Chen Chia-Ray Chen Hung-Wei Chen Hung-Wei Kevin Chen I-Ching Chen Jau-Horng Chen Jia-Yi Chen Yi-Jan Emery Chen Yu-Lin Chen Kai-Ren Cheng Wei-Chih Cheng Hang-Quei Chiu Sen-Wen Hsiao Yi-Chun Hsieh Yao-Sheng Hu Li-Yu Huang Po-Chao Huang Sheng-Hsiang Huang Yen-Chih Huang Chien-Ping Hung A. Ito Chieh-Fan Lai Mickaël Lallart Jia-Han Li Chun-Hao Liang David Liang Pei-Kai Liao Tun-Yen Liao Ding-Guo Lin Jhao-Huei Lin Jyun-Cheng Lin Kai-Yue Lin Sen-Wei Lin Pang-Jung Liu Wei-Ting Shen Chi-Huai Shih Bang-Sup Song Chien-Yu Su Hung-Yen Tai Jia-Nan Tai Sharon Isabelle Timotius Cheng-Hsueh Tsai Pao-Yang Tsai Tsung-Han Tsai Chien-Jian Tseng Chien-Kai Tseng Huan-Chieh Tseng Yi-Lun Wang Junyi WuJun-Yi Wu Shih-Wei Wu Wen-Jong Wu Ching-Hua Yang Mi-Ti Yang Wei-Shan Ye Shih-Bo Yu