A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Yusuke Nitta

Osamu Nishii Yoichi Yuyama Masayuki Ito Yoshikazu Kiyoshige Yusuke Nitta Makoto Ishikawa Tetsuya Yamada Junichi Miyakoshi Yasutaka Wada Keiji Kimura Hironori Kasahara Hideo Maejima A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. 663-669 2011 94-C IEICE Trans. Electron. 4 https://doi.org/10.1587/transele.E94.C.663 http://search.ieice.org/bin/summary.php?id=e94-c_4_663 db/journals/ieicet/ieicet94c.html#NishiiYIKNIYMWKKM11

Yoichi Yuyama Masayuki Ito Yoshikazu Kiyoshige Yusuke Nitta Shigezumi Matsui Osamu Nishii Atsushi Hasegawa Makoto Ishikawa Tetsuya Yamada Junichi Miyakoshi Koichi Terada Tohru Nojiri Masashi Satoh Hiroyuki Mizuno Kunio Uchiyama Yasutaka Wada Keiji Kimura Hironori Kasahara Hideo Maejima A 45nm 37.3GOPS/W heterogeneous multi-core SoC. 100-101 2010 ISSCC https://doi.org/10.1109/ISSCC.2010.5434031 conf/isscc/2010 db/conf/isscc/isscc2010.html#YuyamaIKNMNHIYMTNSMUWKKM10

Hiroaki Shikano Masaki Ito Masafumi Onouchi Takashi Todaka Takanobu Tsunoda Tomoyuki Kodama Kunio Uchiyama Toshihiko Odaka Tatsuya Kamei Ei Nagahama Manabu Kusaoke Yusuke Nitta Yasutaka Wada Keiji Kimura Hironori Kasahara Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. 902-910 2008 43 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2008.917531 db/journals/jssc/jssc43.html#ShikanoIOTTKUOK08

Makoto Saen Kenichi Osada Satoshi Misaka Tetsuya Yamada Yoshitaka Tsujimoto Yuki Kondo Tatsuya Kamei Yutaka Yoshida Ei Nagahama Yusuke Nitta Takayasu Ito Tadashi Kameyama Naohiko Irie Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. 296-604 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373411 conf/isscc/2007 db/conf/isscc/isscc2007.html#SaenOMYTKKYNNIKI07

Tetsuya Yamada Masahide Abe Yusuke Nitta Kenji Ogura Manabu Kusaoke Makoto Ishikawa Motokazu Ozawa Kiwamu Takada Fumio Arakawa Osamu Nishii Toshihiro Hattori Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. 287-294 2006 89-C IEICE Trans. Electron. 3 https://doi.org/10.1093/ietele/e89-c.3.287 db/journals/ieicet/ieicet89c.html#YamadaANOKIOTANH06

Tetsuya Yamada Masahide Abe Yusuke Nitta Kenji Ogura Manabu Kusaoke Makoto Ishikawa Motokazu Ozawa Kiwamu Takada Fumio Arakawa Osamu Nishii Toshihiro Hattori Low-Power Design of 90-nm SuperH Processor Core. 258-266 2005 conf/iccd/2005 ICCD https://doi.org/10.1109/ICCD.2005.72 https://doi.ieeecomputersociety.org/10.1109/ICCD.2005.72 db/conf/iccd/iccd2005.html#YamadayANOKIOTANH05 Toshihiro Hattori Yusuke Nitta Mitsuho Seki Susumu Narita Kunio Uchiyama Tsuyoshi Takahashi Ryuichi Satomura Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. 246-249 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277108 https://www.wikidata.org/entity/Q130949250 db/conf/dac/dac98.html#HattoriNSNUTS98

Masato Soga Jun'ichi Toyoda Yusuke Nitta Takeshi Imanaka Masuzo Yanagida Generation of a hierarchical representation for graphic patterns based on grouping. 70-87 1993 24 Syst. Comput. Jpn. 2 https://doi.org/10.1002/scj.4690240207 db/journals/scjapan/scjapan24.html#SogaTNIY93

Masahide Abe Fumio Arakawa Atsushi Hasegawa Toshihiro Hattori Takeshi Imanaka Naohiko Irie Makoto Ishikawa Masaki Ito Masayuki Ito Takayasu Ito Tatsuya Kamei Tadashi Kameyama Hironori Kasahara Keiji Kimura Yoshikazu Kiyoshige Tomoyuki Kodama Yuki Kondo Manabu Kusaoke Hideo Maejima Shigezumi Matsui Satoshi Misaka Junichi Miyakoshi Hiroyuki Mizuno Ei Nagahama Susumu Narita Osamu Nishii Tohru Nojiri Toshihiko Odaka Kenji Ogura Masafumi Onouchi Kenichi Osada Motokazu Ozawa Makoto Saen Masashi Satoh Ryuichi Satomura Mitsuho Seki Hiroaki Shikano Masato Soga Kiwamu Takada Tsuyoshi Takahashi Koichi Terada Takashi Todaka Jun'ichi Toyoda Yoshitaka Tsujimoto Takanobu Tsunoda Kunio Uchiyama Yasutaka Wada Tetsuya Yamada Masuzo Yanagida Yutaka Yoshida Yoichi Yuyama