<?xml version="1.0"?>
<dblpperson name="Jonathan D&#233;chelotte" pid="228/7690" n="3">
<person key="homepages/228/7690" mdate="2018-10-30">
<author pid="228/7690">Jonathan D&#233;chelotte</author>
</person>
<r><article publtype="informal" key="journals/iacr/FyrbiakWDABTP19" mdate="2020-05-11">
<author pid="135/0314">Marc Fyrbiak</author>
<author pid="205/0383">Sebastian Wallat</author>
<author pid="228/7690">Jonathan D&#233;chelotte</author>
<author pid="228/7702">Nils Albartus</author>
<author pid="228/7692">Sinan B&#246;cker</author>
<author pid="23/2353">Russell Tessier</author>
<author pid="p/ChristofPaar">Christof Paar</author>
<title>On the Difficulty of FSM-based Hardware Obfuscation.</title>
<pages>1163</pages>
<year>2019</year>
<volume>2019</volume>
<journal>IACR Cryptol. ePrint Arch.</journal>
<ee type="oa">https://eprint.iacr.org/2019/1163</ee>
<url>db/journals/iacr/iacr2019.html#FyrbiakWDABTP19</url>
</article>
</r>
<r><article key="journals/tches/FyrbiakWDABTP18" mdate="2020-10-26">
<author pid="135/0314">Marc Fyrbiak</author>
<author pid="205/0383">Sebastian Wallat</author>
<author pid="228/7690">Jonathan D&#233;chelotte</author>
<author orcid="0000-0003-2449-1134" pid="228/7702">Nils Albartus</author>
<author pid="228/7692">Sinan B&#246;cker</author>
<author pid="23/2353">Russell Tessier</author>
<author pid="p/ChristofPaar">Christof Paar</author>
<title>On the Difficulty of FSM-based Hardware Obfuscation.</title>
<pages>293-330</pages>
<year>2018</year>
<volume>2018</volume>
<journal>IACR Trans. Cryptogr. Hardw. Embed. Syst.</journal>
<number>3</number>
<ee type="oa">https://doi.org/10.13154/tches.v2018.i3.293-330</ee>
<url>db/journals/tches/tches2018.html#FyrbiakWDABTP18</url>
</article>
</r>
<r><inproceedings key="conf/fpl/DechelotteTDC18" mdate="2023-03-24">
<author pid="228/7690">Jonathan D&#233;chelotte</author>
<author pid="23/2353">Russell Tessier</author>
<author pid="07/3174">Dominique Dallet</author>
<author pid="50/7863">J&#233;r&#233;mie Crenne</author>
<title>Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping.</title>
<pages>372-375</pages>
<year>2018</year>
<booktitle>FPL</booktitle>
<ee>https://doi.org/10.1109/FPL.2018.00070</ee>
<ee>https://doi.ieeecomputersociety.org/10.1109/FPL.2018.00070</ee>
<crossref>conf/fpl/2018</crossref>
<url>db/conf/fpl/fpl2018.html#DechelotteTDC18</url>
</inproceedings>
</r>
<coauthors n="8" nc="1">
<co c="0"><na f="a/Albartus:Nils" pid="228/7702">Nils Albartus</na></co>
<co c="0"><na f="b/B=ouml=cker:Sinan" pid="228/7692">Sinan B&#246;cker</na></co>
<co c="0"><na f="c/Crenne:J=eacute=r=eacute=mie" pid="50/7863">J&#233;r&#233;mie Crenne</na></co>
<co c="0"><na f="d/Dallet:Dominique" pid="07/3174">Dominique Dallet</na></co>
<co c="0"><na f="f/Fyrbiak:Marc" pid="135/0314">Marc Fyrbiak</na></co>
<co c="0"><na f="p/Paar:Christof" pid="p/ChristofPaar">Christof Paar</na></co>
<co c="0"><na f="t/Tessier:Russell" pid="23/2353">Russell Tessier</na></co>
<co c="0"><na f="w/Wallat:Sebastian" pid="205/0383">Sebastian Wallat</na></co>
</coauthors>
</dblpperson>

