<?xml version="1.0"?>
<dblpperson name="Hyoungcheol Kwon" pid="227/9683" n="1">
<person key="homepages/227/9683" mdate="2018-10-16">
<author pid="227/9683">Hyoungcheol Kwon</author>
</person>
<r><article key="journals/mr/CilentoYTLMLKSL18" mdate="2025-01-19">
<author pid="30/8565">Tommaso Cilento</author>
<author pid="227/9775">Chan-Su Yun</author>
<author pid="227/9593">Arsen Terterian</author>
<author orcid="0000-0002-8768-9423" pid="227/9236">Chang Hwi Lee</author>
<author pid="227/9369">Jung Eon Moon</author>
<author pid="227/9459">Si Woo Lee</author>
<author pid="227/9683">Hyoungcheol Kwon</author>
<author pid="227/9676">Manho Seung</author>
<author pid="227/9366">Seokkiu Lee</author>
<title>Investigation of layout effects in diode-triggered SCRs under very-fast TLP stress through full-size, calibrated 3D TCAD simulation.</title>
<pages>1103-1107</pages>
<year>2018</year>
<volume>88-90</volume>
<journal>Microelectron. Reliab.</journal>
<ee>https://doi.org/10.1016/j.microrel.2018.07.064</ee>
<ee>https://www.wikidata.org/entity/Q129164829</ee>
<url>db/journals/mr/mr88.html#CilentoYTLMLKSL18</url>
</article>
</r>
<coauthors n="8" nc="1">
<co c="0"><na f="c/Cilento:Tommaso" pid="30/8565">Tommaso Cilento</na></co>
<co c="0"><na f="l/Lee:Chang_Hwi" pid="227/9236">Chang Hwi Lee</na></co>
<co c="0"><na f="l/Lee:Seokkiu" pid="227/9366">Seokkiu Lee</na></co>
<co c="0"><na f="l/Lee:Si_Woo" pid="227/9459">Si Woo Lee</na></co>
<co c="0"><na f="m/Moon:Jung_Eon" pid="227/9369">Jung Eon Moon</na></co>
<co c="0"><na f="s/Seung:Manho" pid="227/9676">Manho Seung</na></co>
<co c="0"><na f="t/Terterian:Arsen" pid="227/9593">Arsen Terterian</na></co>
<co c="0"><na f="y/Yun:Chan=Su" pid="227/9775">Chan-Su Yun</na></co>
</coauthors>
</dblpperson>

