<?xml version="1.0"?>
<dblpperson name="M. V. N. V. Prasad" pid="227/1908" n="1">
<person key="homepages/227/1908" mdate="2018-10-02">
<author pid="227/1908">M. V. N. V. Prasad</author>
</person>
<r><article key="journals/vlsisp/RayPD18" mdate="2020-03-12">
<author orcid="0000-0002-7345-1377" pid="47/1007">Kailash Chandra Ray</author>
<author pid="227/1908">M. V. N. V. Prasad</author>
<author pid="53/2455">Anindya Sundar Dhar</author>
<title>An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.</title>
<pages>1569-1580</pages>
<year>2018</year>
<volume>90</volume>
<journal>J. Signal Process. Syst.</journal>
<number>11</number>
<ee>https://doi.org/10.1007/s11265-017-1281-3</ee>
<url>db/journals/vlsisp/vlsisp90.html#RayPD18</url>
</article>
</r>
<coauthors n="2" nc="1">
<co c="0"><na f="d/Dhar:Anindya_Sundar" pid="53/2455">Anindya Sundar Dhar</na></co>
<co c="0"><na f="r/Ray:Kailash_Chandra" pid="47/1007">Kailash Chandra Ray</na></co>
</coauthors>
</dblpperson>

