ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.

Xuan-Yu Lin

Po-Hao Wang Yung-Chen Chien Shang-Jen Tsai Xuan-Yu Lin Rizal Tanjung Yi-Sian Lin Shu-Wei Syu Tay-Jyi Lin Jinn-Shyan Wang Tien-Fu Chen ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. 3341-3354 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2016.2642170 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2016.2642170 db/journals/tvlsi/tvlsi25.html#WangCTLTLSLWC17

Pei-Yuan Chou I-Chen Wu Jai-Wei Lin Xuan-Yu Lin Tien-Fu Chen Tay-Jyi Lin Jinn-Shyan Wang Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. 1-4 2015 ASICON https://doi.org/10.1109/ASICON.2015.7517050 conf/asicon/2015 db/conf/asicon/asicon2015.html#ChouWLLCLW15 Tien-Fu Chen Yung-Chen Chien Pei-Yuan Chou Jai-Wei Lin Tay-Jyi Lin Yi-Sian Lin Shu-Wei Syu Rizal Tanjung Shang-Jen Tsai Jinn-Shyan Wang Po-Hao Wang I-Chen Wu