An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.

Milena Ivanov

Timothy M. Hollis Ronny Schneider Martin Brox Thomas Hein Wolfgang Spirkl Martin Bach Mani Balakrishnan Stefan Dietrich Fabien Funfrock Milena Ivanov Natalija Jovanovic Maksim Kuzmenka Daniel Lauber Juan Ocon Garrido David Ovard Karl Pfefferl Sven Piatkowski Gabriele Piscopo Manfred Plan Jens Polney Jan Pottgiesser Stephan Rau Filippo Vitale Marc Walter Marcos Alvarez Gonzalez Cristian Chetreanu Andrea Sorrentino Jörg Weller Peter Mayer 0003 Michael Richter 0003 Casto Salobrena Garcia Andreas Schneider Shih Nern Wong An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling. 224-235 2022 57 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2021.3104093 db/journals/jssc/jssc57.html#HollisSBHSBBDFI22

Timothy M. Hollis Ronny Schneider Martin Brox Thomas Hein Wolfgang Spirkl Martin Bach Mani Balakrishnan Stefan Dietrich Fabien Funfrock Milena Ivanov Natalija Jovanovic Maksim Kuzmenka Daniel Lauber Juan Ocon Garrido David Ovard Karl Pfefferl Sven Piatkowski Gabriele Piscopo Manfred Plan Jens Polney Jan Pottgiesser Stephan Rau Filippo Vitale Marc Walter Marcos Alvarez Gonzalez Martin Broschwitz Cristian Chetreanu Andrea Sorrentino Jörg Weller Peter Mayer 0003 Michael Richter 0003 Casto Salobrena Garcia Andreas Schneider Shih Nern Wong 25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling. 348-350 2021 ISSCC https://doi.org/10.1109/ISSCC42613.2021.9365925 conf/isscc/2021 db/conf/isscc/isscc2021.html#HollisSBHSBBDFI21

Martin Brox Mani Balakrishnan Martin Broschwitz Cristian Chetreanu Stefan Dietrich Fabien Funfrock Marcos Alvarez Gonzalez Thomas Hein Eugen Huber Daniel Lauber Milena Ivanov Maksim Kuzmenka Chris Mohr Juan Ocon Garrido Swetha Padaraju Sven Piatkowski Jan Pottgiesser Peter Pfefferl Manfred Plan Jens Polney Stephan Rau Michael Richter 0003 Ronny Schneider Ralf Oliver Seitter Wolfgang Spirkl Marc Walter Jörg Weller Filippo Vitale An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. 134-143 2018 53 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2017.2737945 db/journals/jssc/jssc53.html#BroxBBCDFGHHLIK18

Martin Brox Mani Balakrishnan Martin Broschwitz Cristian Chetreanu Stefan Dietrich Fabien Funfrock Marcos Alvarez Gonzalez Thomas Hein Eugen Huber Daniel Lauber Milena Ivanov Maksim Kuzmenka Chris Mohr Francisco Emiliano Munoz Juan Ocon Garrido Swetha Padaraju Sven Piatkowski Jan Pottgiesser Peter Pfefferl Manfred Plan Jens Polney Stefan Rau Michael Richter 0003 Ronny Schneider Ralf Oliver Seitter Wolfgang Spirkl Marc Walter Jörg Weller Filippo Vitale 23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications. 388-389 2017 ISSCC https://doi.org/10.1109/ISSCC.2017.7870424 conf/isscc/2017 db/conf/isscc/isscc2017.html#BroxBBCDFGHHLIK17

Stefan Dietrich Michael Angerbauer Milena Ivanov Dietmar Gogl Heinz Hoenigschmid Michael Kund Corvin Liaw Michael Markert Ralf Symanczyk Laith Altimime Serge Bournat Gerhard Müller A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control. 839-845 2007 42 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2007.892207 db/journals/jssc/jssc42.html#DietrichAIGHKLM07

Laith Altimime Michael Angerbauer Martin Bach Mani Balakrishnan Serge Bournat Martin Broschwitz Martin Brox Cristian Chetreanu Stefan Dietrich Fabien Funfrock Casto Salobrena Garcia Juan Ocon Garrido Dietmar Gogl Marcos Alvarez Gonzalez Thomas Hein Heinz Hoenigschmid Timothy M. Hollis Eugen Huber Natalija Jovanovic Michael Kund Maksim Kuzmenka Daniel Lauber Corvin Liaw Michael Markert Peter Mayer 0003 Chris Mohr Gerhard Müller Francisco Emiliano Munoz David Ovard Swetha Padaraju Karl Pfefferl Peter Pfefferl Sven Piatkowski Gabriele Piscopo Manfred Plan Jens Polney Jan Pottgiesser Stefan Rau Stephan Rau Michael Richter 0003 Andreas Schneider Ronny Schneider Ralf Oliver Seitter Andrea Sorrentino Wolfgang Spirkl Ralf Symanczyk Filippo Vitale Marc Walter Jörg Weller Shih Nern Wong