Insights into FPGA configuration security.

Maik Ender https://orcid.org/0000-0002-0685-2541 https://www.wikidata.org/entity/Q130892142 Maik Ender Insights into FPGA configuration security. 2025 Ruhr University Bochum, Germany https://hss-opus.ub.ruhr-uni-bochum.de/opus4/frontdoor/index/index/docId/12978 https://nbn-resolving.org/urn:nbn:de:hbz:294-129782 https://d-nb.info/1364313367 Simon Klix Felix Hahn Maik Ender Nils Albartus Christof Paar Russell Tessier Silicon Heist: (Ransom) Attacks for AMD Cloud FPGAs via Privilege Escalation. Zenodo 2025 August https://doi.org/10.5281/zenodo.16950451 streams/repo/zenodo

Maik Ender Felix Hahn Marc Fyrbiak Amir Moradi 0001 Christof Paar JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. 426-450 2024 2024 IACR Trans. Cryptogr. Hardw. Embed. Syst. 2 https://doi.org/10.46586/tches.v2024.i2.426-450 db/journals/tches/tches2024.html#EnderHFMP24

Nils Albartus Maik Ender Jan-Niklas Möller Marc Fyrbiak Christof Paar Russell Tessier On the Malicious Potential of Xilinx's Internal Configuration Access Port (ICAP). 26:1-26:28 2024 June 17 ACM Trans. Reconfigurable Technol. Syst. 2 https://doi.org/10.1145/3633204 https://www.wikidata.org/entity/Q130892145 db/journals/trets/trets17.html#AlbartusEMFPT24

Endres Puschner Maik Ender Steffen Becker 0003 Christof Paar Patching FPGAs: The Security Implications of Bitstream Modifications. 89-99 2024 ASHES@CCS https://doi.org/10.1145/3689939.3695779 conf/ashes/2024 db/conf/ashes/ashes2024.html#PuschnerE0P24

Maik Ender Felix Hahn Marc Fyrbiak Amir Moradi 0001 Christof Paar JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. 2024 abs/2402.09845 CoRR https://doi.org/10.48550/arXiv.2402.09845 db/journals/corr/corr2402.html#abs-2402-09845

Endres Puschner Maik Ender Steffen Becker 0003 Christof Paar Patching FPGAs: The Security Implications of Bitstream Modifications. 2024 abs/2411.11060 CoRR https://doi.org/10.48550/arXiv.2411.11060 db/journals/corr/corr2411.html#abs-2411-11060 streams/journals/corr

Nils Albartus Maik Ender Jan-Niklas Möller Marc Fyrbiak Christof Paar Russell Tessier On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP). 1 2023 ICFPT https://doi.org/10.1109/ICFPT59805.2023.00059 conf/fpt/2023 db/conf/fpt/icfpt2023.html#AlbartusEMFPT23 Susanne Engels Maik Ender Christof Paar Targeted Bitstream Fault Fuzzing Accelerating BiFI on Large Designs. 13-23 2023 HOST https://doi.org/10.1109/HOST55118.2023.10133494 conf/host/2023 db/conf/host/host2023.html#EngelsEP23

Anita Aghaie Maik Ender Amir Moradi 0001 PUFs Physical Learning: Accelerating the Enrollment via Delay-Based Model Extraction. 1621-1632 2022 10 IEEE Trans. Emerg. Top. Comput. 3 https://doi.org/10.1109/TETC.2021.3115176 db/journals/tetc/tetc10.html#AghaieEM22

Maik Ender Gregor Leander Amir Moradi 0001 Christof Paar A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine. 1-9 2022 FCCM https://doi.org/10.1109/FCCM53951.2022.9786118 conf/fccm/2022 db/conf/fccm/fccm2022.html#EnderLMP22 Julian Speith Florian Schweins Maik Ender Marc Fyrbiak Alexander May 0001 Christof Paar How Not to Protect Your IP - An Industry-Wide Break of IEEE 1735 Implementations. 1656-1671 2022 SP https://doi.org/10.1109/SP46214.2022.9833605 conf/sp/2022 db/conf/sp/sp2022.html#SpeithSEF0P22

Maik Ender Amir Moradi 0001 Christof Paar The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs. 2021 abs/2105.13756 CoRR https://arxiv.org/abs/2105.13756 db/journals/corr/corr2105.html#abs-2105-13756

Julian Speith Florian Schweins Maik Ender Marc Fyrbiak Alexander May 0001 Christof Paar How Not to Protect Your IP - An Industry-Wide Break of IEEE 1735 Implementations. 2021 abs/2112.04838 CoRR https://arxiv.org/abs/2112.04838 db/journals/corr/corr2112.html#abs-2112-04838

Julian Speith Steffen Becker 0003 Maik Ender Endres Puschner Christof Paar Hardware-Trojaner. 446-450 2020 44 Datenschutz und Datensicherheit 7 https://doi.org/10.1007/s11623-020-1303-3 db/journals/dud/dud44.html#SpeithBEPP20

Maik Ender Amir Moradi 0001 Christof Paar The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs. 1803-1819 2020 USENIX Security Symposium https://www.usenix.org/conference/usenixsecurity20/presentation/ender conf/uss/2020 db/conf/uss/uss2020.html#Ender0P20 Maik Ender Pawel Swierczynski Sebastian Wallat Matthias Wilhelm 0002 Paul Martin Knopp Christof Paar Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream. 112-119 2019 ASP-DAC https://doi.org/10.1145/3287624.3288742 conf/aspdac/2019 db/conf/aspdac/aspdac2019.html#EnderSWWKP19 Sebastian Wallat Nils Albartus Steffen Becker 0003 Max Hoffmann 0001 Maik Ender Marc Fyrbiak Adrian Drees Sebastian Maaßen Christof Paar Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework. 392-397 2019 CF https://doi.org/10.1145/3310273.3323419 conf/cf/2019 db/conf/cf/cf2019.html#WallatA00EFDMP19

Sebastian Wallat Nils Albartus Steffen Becker 0003 Max Hoffmann 0001 Maik Ender Marc Fyrbiak Adrian Drees Sebastian Maaßen Christof Paar Highway to HAL: Open-Sourcing the First Extendable Gate-Level Netlist Reverse Engineering Framework. 2019 abs/1910.00350 CoRR http://arxiv.org/abs/1910.00350 db/journals/corr/corr1910.html#abs-1910-00350

Maik Ender Pawel Swierczynski Sebastian Wallat Matthias Wilhelm 0002 Paul Martin Knopp Christof Paar Insights into the Mind of a Trojan Designer: The Challenge to Integrate a Trojan into the Bitstream. 2019 abs/1910.01517 CoRR http://arxiv.org/abs/1910.01517 db/journals/corr/corr1910.html#abs-1910-01517

Thomas De Cnudde Maik Ender Amir Moradi 0001 Hardware Masking, Revisited. 123-148 2018 2018 IACR Trans. Cryptogr. Hardw. Embed. Syst. 2 https://doi.org/10.13154/tches.v2018.i2.123-148 db/journals/tches/tches2018.html#CnuddeEM18

Maik Ender Samaneh Ghandali Amir Moradi 0001 Christof Paar The First Thorough Side-Channel Hardware Trojan. 755-780 2017 ASIACRYPT (1) https://doi.org/10.1007/978-3-319-70694-8_26 conf/asiacrypt/2017-1 db/conf/asiacrypt/asiacrypt2017-1.html#EnderG0P17 Maik Ender Alexander Wild Amir Moradi 0001 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA. 83-101 2017 COSADE https://doi.org/10.1007/978-3-319-64647-3_6 conf/cosade/2017 db/conf/cosade/cosade2017.html#EnderW017

Maik Ender Alexander Wild Amir Moradi 0001 SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA. 284 2017 2017 IACR Cryptol. ePrint Arch. http://eprint.iacr.org/2017/284 db/journals/iacr/iacr2017.html#EnderWM17

Maik Ender Samaneh Ghandali Amir Moradi 0001 Christof Paar The First Thorough Side-Channel Hardware Trojan. 865 2017 2017 IACR Cryptol. ePrint Arch. http://eprint.iacr.org/2017/865 db/journals/iacr/iacr2017.html#EnderG0P17

Maik Ender Gerd Duppmann Alexander Wild Thomas Pöppelmann Tim Güneysu A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems. 1-6 2014 ReConFig https://doi.org/10.1109/ReConFig.2014.7032489 conf/reconfig/2014 db/conf/reconfig/reconfig2014.html#EnderDWPG14 Anita Aghaie Nils Albartus Steffen Becker 0003 Thomas De Cnudde Adrian Drees Gerd Duppmann Susanne Engels Marc Fyrbiak Samaneh Ghandali Tim Güneysu Felix Hahn Max Hoffmann 0001 Simon Klix Paul Martin Knopp Gregor Leander Sebastian Maaßen Alexander May 0001 Jan-Niklas Möller Amir Moradi 0001 Christof Paar Thomas Pöppelmann Endres Puschner Florian Schweins Julian Speith Pawel Swierczynski Russell Tessier Sebastian Wallat Alexander Wild Matthias Wilhelm 0002