A Formal Y86 Simulator with CHERI Features.

William D. Young University of Texas at Austin, USA http://www.cs.utexas.edu/~byoung/ Carl Kwan Yutong Xin William D. Young A Formal Y86 Simulator with CHERI Features. 2025 FMCAD https://doi.org/10.34727/2025/isbn.978-3-85448-084-6_22 conf/fmcad/2025 db/conf/fmcad/fmcad2025.html#KwanXY25 William D. Young Modeling Asymptotic Complexity Using ACL2. ACL2 2022 83-98 journals/corr/abs-2205-11103 https://doi.org/10.4204/EPTCS.359.9 https://doi.org/10.48550/arXiv.2205.11700 db/series/eptcs/eptcs359.html#abs-2205-11700 Michael McCoyd Robert Bellarmine Krug Deepak Goel Mike Dahlin William D. Young Building a Hypervisor on a Formally Verifiable Protection Layer. 5069-5078 2013 HICSS https://doi.org/10.1109/HICSS.2013.121 https://doi.ieeecomputersociety.org/10.1109/HICSS.2013.121 conf/hicss/2013 db/conf/hicss/hicss2013.html#McCoydKGDY13 Mike Dahlin Ryan Johnson 0003 Robert Bellarmine Krug Michael McCoyd William D. Young Toward the Verification of a Simple Hypervisor ACL2 2011 28-45 https://doi.org/10.4204/EPTCS.70.3 http://arxiv.org/abs/1110.4672 journals/corr/abs-1110-4473 db/series/eptcs/eptcs70.html#abs-1110-4672 Warren A. Hunt Jr. Robert Bellarmine Krug Sandip Ray William D. Young Mechanized Information Flow Analysis through Inductive Assertions. 1-4 2008 FMCAD https://doi.org/10.1109/FMCAD.2008.ECP.33 conf/fmcad/2008 db/conf/fmcad/fmcad2008.html#HuntKRY08 David S. Hardin Eric Whitman Smith William D. Young A robust machine code proof framework for highly secure applications. 11-20 2006 conf/acl2/2006 ACL2 https://doi.org/10.1145/1217975.1217978 https://www.wikidata.org/entity/Q130981546 db/conf/acl2/acl22006.html#HardinSY06 William D. Young Introducing Abstractions via Rewriting. 402-405 2005 conf/charme/2005 CHARME https://doi.org/10.1007/11560548_41 db/conf/charme/charme2005.html#Young05

William D. Young Comparing Verification Systems: Interactive Consistency in ACL2. 214-223 https://doi.org/10.1109/32.588536 http://doi.ieeecomputersociety.org/10.1109/32.588536 1997 23 IEEE Trans. Software Eng. 4 db/journals/tse/tse23.html#Young97

William D. Young William R. Bevier Mathematical Modeling and Analysis of an External Memory Manager. 237-257 1997 conf/fm/1997 FME db/conf/fm/fme1997.html#YoungB97 https://doi.org/10.1007/3-540-63533-5_13

William R. Bevier William D. Young A State-Machine Approach to Non-Interference. 55-70 1995 3 J. Comput. Secur. 1 db/journals/jcs/jcs3.html#BevierY95 https://doi.org/10.3233/JCS-1994/1995-3105 https://www.wikidata.org/entity/Q114944555

William R. Bevier Richard M. Cohen William D. Young Connection policies and controlled interference. 167-176 1995 conf/csfw/1995 CSFW https://doi.org/10.1109/CSFW.1995.518561 https://doi.ieeecomputersociety.org/10.1109/CSFW.1995.518561 db/conf/csfw/csfw1995.html#BevierCY95 William D. Young William R. Bevier A State-Based Approach to Non-Interference. 1994 conf/csfw/1994 CSFW db/conf/csfw/csfw1994.html#YoungB94 11-21 https://doi.org/10.1109/CSFW.1994.315951

William R. Bevier William D. Young Machine Checked Proofs of the Design of a Fault-Tolerance Circuit. 755-775 1992 4 Formal Aspects Comput. 6A db/journals/fac/fac4.html#BevierY92

Bishop Brock Warren A. Hunt Jr. William D. Young Introduction to a Formally Defined Hardware Description Language. 3-35 1992 conf/tpcd/1992 TPCD db/conf/tpcd/tpcd1992.html#BrockHY92 Donald I. Good William D. Young Mathematical Methods for Digital Systems Development. 406-430 1991 conf/fm/1991-2 VDM Europe (2) db/conf/fm/vdme1991-2.html#GoodY91 https://doi.org/10.1007/BFb0020002 William D. Young Formal Methods versus Software Engineering: Is There a Conflict? 188-189 1991 conf/issta/1991 Symposium on Testing, Analysis, and Verification https://doi.org/10.1145/120807.120824 db/conf/issta/tav91.html#Young91 William D. Young Verified program support environments. 147-149 1990 Formal Methods in Software Development https://doi.org/10.1145/99569.99839 https://doi.org/10.1145/99571.99839 conf/fmsd/1990 db/conf/fmsd/fmsd1990.html#Young90

William R. Bevier Warren A. Hunt Jr. J Strother Moore William D. Young An Approach to Systems Verification. 411-428 1989 5 J. Autom. Reason. 4 db/journals/jar/jar5.html#BevierHMY89 https://doi.org/10.1007/BF00243131

William D. Young A Mechanically Verified Code Generator. 493-518 1989 5 J. Autom. Reason. 4 db/journals/jar/jar5.html#Young89 https://doi.org/10.1007/BF00243134

William D. Young Verified Compilation in micro-Gypsy. 20-26 1989 conf/issta/1989 Symposium on Testing, Analysis, and Verification https://doi.org/10.1145/75308.75312 https://doi.org/10.1145/75309.75312 db/conf/issta/tav89.html#Young89

J. Thomas Haigh William D. Young Extending the Noninterference Version of MLS for SAT. 141-150 1987 13 IEEE Trans. Software Eng. 2 db/journals/tse/tse13.html#HaighY87 https://doi.org/10.1109/TSE.1987.226478 http://doi.ieeecomputersociety.org/10.1109/TSE.1987.226478

J. Thomas Haigh Richard A. Kemmerer John McHugh William D. Young An Experience Using Two Covert Channel Analysis Techniques on a Real System Design. 157-168 1987 13 IEEE Trans. Software Eng. 2 db/journals/tse/tse13.html#HaighKMY87 https://doi.org/10.1109/TSE.1987.226479 http://doi.ieeecomputersociety.org/10.1109/TSE.1987.226479 https://www.wikidata.org/entity/Q111898929

William R. Bevier Warren A. Hunt Jr. William D. Young Toward Verified Execution Environments. 106-115 1987 conf/sp/1987 S&P db/conf/sp/sp1987.html#BevierHY87 https://doi.org/10.1109/SP.1987.10018 https://doi.ieeecomputersociety.org/10.1109/SP.1987.10018 William D. Young John McHugh Coding for a Believable Specification to Implementation Mapping. 140-149 1987 conf/sp/1987 S&P db/conf/sp/sp1987.html#YoungM87 https://doi.org/10.1109/SP.1987.10003 https://doi.ieeecomputersociety.org/10.1109/SP.1987.10003 J. Thomas Haigh Richard A. Kemmerer John McHugh William D. Young An Experience Using Two Covert Channel Analysis Techniques on a Real System Design. 14-24 1986 conf/sp/1986 S&P db/conf/sp/sp1986.html#HaighKMY86 https://doi.org/10.1109/SP.1986.10013 https://doi.ieeecomputersociety.org/10.1109/SP.1986.10013 J. Thomas Haigh William D. Young Extending the Non-Interference Version of MLS for SAT. 60 1986 conf/sp/1986 S&P db/conf/sp/sp1986.html#HaighY86 https://doi.org/10.1109/SP.1986.10004 https://doi.ieeecomputersociety.org/10.1109/SP.1986.10004 William Earl Boebert R. Y. Kaln William D. Young S. A. Hansohn Secure Ada Target: Issues, System Design, and Verification. 176-183 1985 S&P https://doi.org/10.1109/SP.1985.10022 https://doi.ieeecomputersociety.org/10.1109/SP.1985.10022 conf/sp/1985 db/conf/sp/sp1985.html#BoebertKYH85

William D. Young Donald I. Good Steelman and the verifiability of (preliminary) ADA. 113-119 1981 16 ACM SIGPLAN Notices 2 https://doi.org/10.1145/954269.954286 db/journals/sigplan/sigplan16.html#YoungG81

Anand R. Tripathi William D. Young Donald I. Good James C. Browne HAL/S/V: a verifiable subset for HAL/S. 102-112 1981 16 ACM SIGPLAN Notices 3 https://doi.org/10.1145/947825.947833 db/journals/sigplan/sigplan16.html#TripathiYGB81

Anand R. Tripathi William D. Young Donald I. Good A preliminary evaluation of verifiability in Ada. 218-224 1980 ACM Annual Conference https://doi.org/10.1145/800176.809971 conf/acm/1980 db/conf/acm/acm1980.html#TripathiYG80 William D. Young Donald I. Good Generics and verification in Ada. 123-127 1980 SIGPLAN https://doi.org/10.1145/800004.807942 https://doi.org/10.1145/948632.948649 https://doi.org/10.1145/947783.948649 conf/sigplan/1980 db/conf/sigplan/sigplan1980.html#YoungG80 William R. Bevier William Earl Boebert Bishop Brock James C. Browne Richard M. Cohen Michael DahlinMike Dahlin Deepak Goel Donald I. Good J. Thomas Haigh S. A. Hansohn David S. Hardin Warren A. Hunt Jr. Ryan Johnson 0003 R. Y. Kaln Richard A. Kemmerer Robert Bellarmine Krug Carl Kwan Michael McCoyd John McHugh J Strother Moore Sandip Ray Eric Whitman Smith Anand R. Tripathi Yutong Xin