Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions.

Sayed Masoud Sayedi Masoud Sayedi

Zahra Mehdizadeh Taheri Sayed Masoud Sayedi Mohammad Hossein Moaiyeri Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions. 49076-49091 2025 13 IEEE Access https://doi.org/10.1109/ACCESS.2025.3551411 db/journals/access/access13.html#TaheriSM25 streams/journals/access

Elias Rajaby Sayed Masoud Sayedi Ehsan Yazdian Hardware design and implementation of high-efficiency cube-root of complex numbers. 104847 2023 July 100 Microprocess. Microsystems https://doi.org/10.1016/j.micpro.2023.104847 db/journals/mam/mam100.html#RajabySY23

Elias Rajaby Sayed Masoud Sayedi A structured review of sparse fast Fourier transform algorithms. 103403 2022 123 Digit. Signal Process. https://doi.org/10.1016/j.dsp.2022.103403 db/journals/dsp/dsp123.html#RajabyS22

Mohammad Radpour Sayed Masoud Sayedi SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor. 48-55 2018 60 Integr. https://doi.org/10.1016/j.vlsi.2017.08.006 db/journals/integration/integration60.html#RadpourS18

Mohammad Fardad Sayed Masoud Sayedi Ehsan Yazdian A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction. 3349-3361 2018 65-I IEEE Trans. Circuits Syst. I Regul. Pap. 10 https://doi.org/10.1109/TCSI.2018.2803627 https://www.wikidata.org/entity/Q130204109 db/journals/tcas/tcasI65.html#FardadSY18

Mohammad Fardad Sayed Masoud Sayedi Ehsan Yazdian Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals. 867-877 2018 26 IEEE Trans. Very Large Scale Integr. Syst. 5 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2791351 db/journals/tvlsi/tvlsi26.html#FardadSY18

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems. 103-112 2017 11 IET Circuits Devices Syst. 2 https://doi.org/10.1049/iet-cds.2015.0337 db/journals/iet-cds/iet-cds11.html#RashidiSF17

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications. 568-578 2017 11 IET Circuits Devices Syst. 6 https://doi.org/10.1049/iet-cds.2017.0110 db/journals/iet-cds/iet-cds11.html#RashidiSF17a

Bahram Rashidi Reza Rezaeian Farashahi Sayed Masoud Sayedi High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m ). 66-77 2017 11 IET Inf. Secur. 2 https://doi.org/10.1049/iet-ifs.2015.0461 db/journals/iet-ifs/iet-ifs11.html#RashidiFS17

Mohammad Reza Mahmoodi Sayed Masoud Sayedi Fariba Karimi 0003 Color-based skin segmentation in videos using a multi-step spatial method. 9785-9801 2017 76 Multim. Tools Appl. 7 https://doi.org/10.1007/s11042-016-3579-8 db/journals/mta/mta76.html#MahmoodiSK17

Bahram Rashidi Reza Rezaeian Farashahi Sayed Masoud Sayedi High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves. 5 2017 2017 IACR Cryptol. ePrint Arch. http://eprint.iacr.org/2017/005 db/journals/iacr/iacr2017.html#RashidiFS17

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m ). 18-29 2016 10 IET Comput. Digit. Tech. 1 https://doi.org/10.1049/iet-cdt.2015.0020 db/journals/iet-cdt/iet-cdt10.html#RashidiSF16

Kourosh Hassanli Sayed Masoud Sayedi Rasoul Dehghani Armin Jalili J. Jacob Wikner A low-power wide tuning-range CMOS current-controlled oscillator. 57-66 2016 55 Integr. https://doi.org/10.1016/j.vlsi.2016.03.001 db/journals/integration/integration55.html#HassanliSDJW16

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m). 138-154 2016 55 Integr. https://doi.org/10.1016/j.vlsi.2016.05.006 db/journals/integration/integration55.html#RashidiSF16

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. 49-65 2016 52 Microelectron. J. https://doi.org/10.1016/j.mejo.2016.03.006 db/journals/mj/mj52.html#RashidiSF16

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m). 966 2016 2016 IACR Cryptol. ePrint Arch. http://eprint.iacr.org/2016/966 db/journals/iacr/iacr2016.html#RashidiSF16

Mohammad Reza Mahmoodi Sayed Masoud Sayedi A face detection method based on kernel probability map. 205-216 2015 46 Comput. Electr. Eng. https://doi.org/10.1016/j.compeleceng.2015.02.005 db/journals/cee/cee46.html#MahmoodiS15

Bahram Rashidi Reza Rezaeian Farashahi Sayed Masoud Sayedi Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. 101-114 2015 7 ISC Int. J. Inf. Secur. 2 https://doi.org/10.22042/isecure.2016.7.2.3 db/journals/isecure/isecure7.html#RashidiFS15

Bahram Rashidi Sayed Masoud Sayedi Reza Rezaeian Farashahi Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems. 1109 2015 2015 IACR Cryptol. ePrint Arch. http://eprint.iacr.org/2015/1109 db/journals/iacr/iacr2015.html#RashidiSF15

Reza Rezaeian Farashahi Bahram Rashidi Sayed Masoud Sayedi FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. 1014-1025 2014 45 Microelectron. J. 8 https://doi.org/10.1016/j.mejo.2014.05.004 https://www.wikidata.org/entity/Q122166430 db/journals/mj/mj45.html#FarashahiRS14

Bahram Rashidi Reza Rezaeian Farashahi Sayed Masoud Sayedi High-speed and pipelined finite field bit-parallel multiplier over GF(2m) for elliptic curve cryptosystems. 15-20 2014 ISCISC https://doi.org/10.1109/ISCISC.2014.6994015 conf/iscisc/2014 db/conf/iscisc/iscisc2014.html#RashidiFS14

Shirin Pourashraf Sayed Masoud Sayedi Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure. 1165-1174 2013 44 Microelectron. J. 12 https://doi.org/10.1016/j.mejo.2013.08.001 db/journals/mj/mj44.html#PourashrafS13

Hesam Ahmadi Sayed Masoud Sayedi Design of a neuromorphic edge detector vision chip with color and intensity change disambiguation. 1-5 2012 CCECE https://doi.org/10.1109/CCECE.2012.6334875 conf/ccece/2012 db/conf/ccece/ccece2012.html#AhmadiS12 Mehrnaz Ahmady Sayed Masoud Sayedi Fault coverage improvement and test vector generation for combinational circuits using spectral analysis. 1-5 2012 CCECE https://doi.org/10.1109/CCECE.2012.6334825 conf/ccece/2012 db/conf/ccece/ccece2012.html#AhmadyS12 Shirin Pourashraf Sayed Masoud Sayedi A low power D3L 16-bit radix- 4 pipelined SRT divider. 1-6 2012 CCECE https://doi.org/10.1109/CCECE.2012.6335043 conf/ccece/2012 db/conf/ccece/ccece2012.html#PourashrafS12

Mehdi Habibi Sayed Masoud Sayedi Asynchronous demodulation technique for use in vision sensor image classification and segmentation. 17-30 2011 39 Int. J. Circuit Theory Appl. 1 https://doi.org/10.1002/cta.614 db/journals/ijcta/ijcta39.html#HabibiS11

Armin Jalili Sayed Masoud Sayedi J. Jacob Wikner Abolghasem Zeidaabadi Nezhad A nonlinearity error calibration technique for pipelined ADCs. 229-241 2011 44 Integr. 3 https://doi.org/10.1016/j.vlsi.2011.01.004 db/journals/integration/integration44.html#JaliliSWN11

Armin Jalili Sayed Masoud Sayedi J. Jacob Wikner Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs. 158-164 2011 42 Microelectron. J. 1 https://doi.org/10.1016/j.mejo.2010.08.014 db/journals/mj/mj42.html#JaliliSW11

Mehdi Habibi Masoud Sayedi Geometric centre tracking of tagged objects using a low power demodulation smart vision sensor. 67-77 2010 4 IET Circuits Devices Syst. 1 https://doi.org/10.1049/iet-cds.2008.0244 db/journals/iet-cds/iet-cds4.html#HabibiS10

Hossein Karimiyan Sayed Masoud Sayedi Hossein Saidi 0001 Low-power dual-edge triggered state-retention scan flip-flop. 410-419 2010 4 IET Comput. Digit. Tech. 5 https://doi.org/10.1049/iet-cdt.2009.0059 db/journals/iet-cdt/iet-cdt4.html#KarimiyanSS10

Mehdi Habibi Sayed Masoud Sayedi Asynchronous demodulation CMOS sensor for object labeling and its application in robotics. 62-69 2010 37 Ind. Robot 1 https://doi.org/10.1108/01439911011009966 db/journals/irob/irob37.html#HabibiS10

Armin Jalili Sayed Masoud Sayedi J. Jacob Wikner Kent Palmkvist Mark Vesterbacka Calibration of high-resolution flash ADCS based on histogram test methods. 114-117 2010 ICECS https://doi.org/10.1109/ICECS.2010.5724467 conf/icecsys/2010 db/conf/icecsys/icecsys2010.html#JaliliSWPV10

Mehdi Habibi Masoud Sayedi An Analog VLSI Architecture for High Speed, Low Power Object Tracking. 675-692 2009 5 Int. J. Distributed Sens. Networks 6 https://doi.org/10.1080/15501320802581557 db/journals/ijdsn/ijdsn5.html#HabibiS09

Hossein Karimiyan Sayed Masoud Sayedi Hossein Saidi 0001 Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop. 156-164 2009 PATMOS https://doi.org/10.1007/978-3-642-11802-9_20 conf/patmos/2009 db/conf/patmos/patmos2009.html#KarimiyanSS09

Ebrahim Farshidi Sayed Masoud Sayedi A 1.2 V current-mode true RMS-DC converter based on the floating gate MOS translinear principle. 293-298 2008 39 Microelectron. J. 2 https://doi.org/10.1016/j.mejo.2007.11.022 db/journals/mj/mj39.html#FarshidiS08

Armin Jalili Sayed Masoud Sayedi A nonlinearity error calibration technique based on an opamp distortion modeling. 806-809 2008 APCCAS https://doi.org/10.1109/APCCAS.2008.4746145 conf/apccas/2008 db/conf/apccas/apccas2008.html#JaliliS08 Armin Jalili Sayed Masoud Sayedi Rasoul Dehghani Ebrahim Farshidi A frequency based digital background calibration technique for pipelined ADCs. 1209-1212 2008 ICECS https://doi.org/10.1109/ICECS.2008.4675076 conf/icecsys/2008 db/conf/icecsys/icecsys2008.html#JaliliSDF08 Dawood Shekari Beyragh Sayed Masoud Sayedi Hamid Reza Karshenas A Novel Digital Voltage Controller for Single-Phase PFC Rectifiers. 887-890 2006 conf/ccece/2006 CCECE https://doi.org/10.1109/CCECE.2006.277798 db/conf/ccece/ccece2006.html#BeyraghSK06 Hesam Ahmadi Mehrnaz Ahmady Hossein Karimiyan AlidashHossein Karimiyan Dawood Shekari Beyragh Rasoul Dehghani Reza Rezaeian Farashahi Mohammad Fardad Ebrahim Farshidi Mehdi Habibi Kourosh Hassanli Armin Jalili Fariba Karimi 0003 Hamid Reza Karshenas Mohammad Reza Mahmoodi Mohammad Hossein Moaiyeri Abolghasem Zeidaabadi Nezhad Kent Palmkvist Shirin Pourashraf Mohammad Radpour Elias Rajaby Bahram Rashidi Hossein Saidi 0001 Zahra Mehdizadeh Taheri Mark Vesterbacka J. Jacob Wikner Ehsan Yazdian