A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme.

Akinori Shibayama

Toshikazu Suzuki Yoshinobu Yamagami Ichiro Hatanaka Akinori Shibayama Hironori Akamatsu Hiroyuki Yamauchi A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. 152-160 2006 41 IEEE J. Solid State Circuits 1 https://doi.org/10.1109/JSSC.2005.859029 db/journals/jssc/jssc41.html#SuzukiYHSAY06

Toshikazu Suzuki Yoshinobu Yamagami Ichiro Hatanaka Akinori Shibayama Hironori Akamatsu Hiroyuki Yamauchi 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. 630-638 2005 88-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e88-c.4.630 db/journals/ieicet/ieicet88c.html#SuzukiYHSAY05

Koji Nii Yasumasa Tsukamoto Tomoaki Yoshizawa Susumu Imaoka Yoshinobu Yamagami Toshikazu Suzuki Akinori Shibayama Hiroshi Makino Shuhei Iwade A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. 684-693 2004 39 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2004.825235 db/journals/jssc/jssc39.html#NiiTYIYSSMI04

Hirohito Kikukawa Shigeki Tomishima Takaharu Tsuji Toshiaki Kawasaki Shouji Sakamoto Masatoshi Ishikawa Wataru Abe Hiroaki Tanizaki Hiroshi Kato Toshitaka Uchikoba Toshihiro Inokuchi Manabu Senoh Yoshifumi Fukushima Mitsutaka Niiro Masanao Maruta Akinori Shibayama Tsukasa Ooishi Kazunari Takahashi Hideto Hidaka 0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. 932-940 2002 37 IEEE J. Solid State Circuits 7 https://doi.org/10.1109/JSSC.2002.1015693 db/journals/jssc/jssc37.html#KikukawaTTKSIAT02

Shigeki Tomishima Takaharu Tsuji Toshiaki Kawasaki Masatoshi Ishikawa Toshihiro Inokuchi Hiroshi Kato Hiroaki Tanizaki Wataru Abe Akinori Shibayama Yoshifumi Fukushima Mitsutaka Niiro Masanao Maruta Toshitaka Uchikoba Manabu Senoh Shouji Sakamoto Tsukasa Ooishi Hirohito Kikukawa Hideto Hidaka Kazunari Takahashi A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. 1728-1737 2001 36 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.962295 db/journals/jssc/jssc36.html#TomishimaTKIIKT01

Toshio Yamada Yoshiro Nakata Junko Hasegawa Noriaki Amano Akinori Shibayama Masaru Sasago Naoto Matsuo Toshiki Yabu Susumu Matsumoto Shozo Okada Michihiro Inoue A 64-Mb DRAM with meshed power line. 1506-1510 1991 November 26 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/4.98965 db/journals/jssc/jssc26.html#YamadaNHASSMYMOI91 streams/journals/jssc

Wataru Abe Hironori Akamatsu Noriaki Amano Yoshifumi Fukushima Junko Hasegawa Ichiro Hatanaka Hideto Hidaka Susumu Imaoka Toshihiro Inokuchi Michihiro Inoue Masatoshi Ishikawa Shuhei Iwade Hiroshi Kato Toshiaki Kawasaki Hirohito Kikukawa Hiroshi Makino Masanao Maruta Susumu Matsumoto Naoto Matsuo Yoshiro Nakata Koji Nii Mitsutaka Niiro Shozo Okada Tsukasa Ooishi Shouji Sakamoto Masaru Sasago Manabu Senoh Toshikazu Suzuki Kazunari Takahashi Hiroaki Tanizaki Shigeki Tomishima Takaharu Tsuji Yasumasa Tsukamoto Toshitaka Uchikoba Toshiki Yabu Toshio Yamada Yoshinobu Yamagami Hiroyuki Yamauchi Tomoaki Yoshizawa