Power-aware BTB for modern processors.

Kaveh Jokar Deris

Kaveh Jokar Deris Amirali Baniasadi Power-aware BTB for modern processors. 902-911 2010 36 Comput. Electr. Eng. 5 https://doi.org/10.1016/j.compeleceng.2008.04.008 db/journals/cee/cee36.html#DerisB10

Amirali Baniasadi Babak Salamat Kaveh Jokar Deris Power-aware scoreboard alternatives for multimedia processors. 326-332 2009 33 Microprocess. Microsystems 4 https://doi.org/10.1016/j.micpro.2009.02.012 db/journals/mam/mam33.html#BaniasadiSD09

Kaveh Jokar Deris Amirali Baniasadi Investigating cache energy and latency break-even points in high performance processors. 13-20 2007 35 SIGARCH Comput. Archit. News 4 https://doi.org/10.1145/1327312.1327316 db/journals/sigarch/sigarch35.html#DerisB07

Kaveh Jokar Deris Amirali Baniasadi Investigating cache energy and latency break-even points in high performance processors. 13-20 2006 MEDEA@PACT https://doi.org/10.1145/1166133.1166135 conf/medea/2006 db/conf/medea/medea2006.html#DerisB06 Kaveh Jokar Deris Amirali Baniasadi Branchless cycle prediction for embedded processors. 928-932 2006 conf/sac/2006 SAC https://doi.org/10.1145/1141277.1141492 db/conf/sac/sac2006.html#DerisB06 Babak Salamat Amirali Baniasadi Kaveh Jokar Deris Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors. 50-55 2006 conf/samos/2006ic ICSAMOS https://doi.org/10.1109/ICSAMOS.2006.300808 db/conf/samos/samos2006ic.html#SalamatBD06 Amirali Baniasadi Babak Salamat