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Improving Verilog Four State Logic
How SeqiLog improves the distinction between uninitialized/metastable and "don't care" values
Dec 30, 2024
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Chris Drake
1
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Contrasting Verilog and SeqiLog Port List Customization
How using a Python-based builder pattern to construct Module contents simplifies and expands the possibilities for interfaces.
Dec 8, 2024
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Chris Drake
Logic Simulation, Part 1
First steps with logic simulation using SimPy and pyvcd
May 23, 2023
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Chris Drake
1
Geometric Distribution in SystemVerilog
How to implement the geometric probability distribution in SystemVerilog
Oct 9, 2020
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Chris Drake
Ready/Valid Protocol Primer
An introduction to the ready/valid data transfer protocol
Aug 2, 2020
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Chris Drake
2
Verilog Case Inside Statement
Explore the obscure yet powerful Verilog case inside statement
Jun 29, 2020
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Chris Drake
1
How to Destroy Yourself
Advice on avoiding the road to self destruction
May 12, 2020
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Chris Drake
Verilog Flip-Flop Macros
Proper use of Verilog flop macros, and their surprising tradeoffs
Aug 23, 2014
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Chris Drake
1
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