{"id":477,"date":"2019-10-01T17:15:56","date_gmt":"2019-10-01T11:45:56","guid":{"rendered":"https:\/\/binaryterms.com\/?p=477"},"modified":"2021-01-18T13:00:42","modified_gmt":"2021-01-18T07:30:42","slug":"risc-processor","status":"publish","type":"post","link":"https:\/\/binaryterms.com\/risc-processor.html","title":{"rendered":"RISC Processor"},"content":{"rendered":"

RISC<\/strong> is an abbreviation of Reduced Instruction Set Computer<\/strong>. RISC processor has ‘instruction sets’ that are simple and have simple ‘addressing modes’. A RISC style instruction engages “one word” in memory. Execution of the RISC instructions are faster<\/strong> and take one clock cycle<\/strong> per instruction.<\/p>\n

Although the forerunners of RISC computers were seen in 1960<\/strong>. But, due to the popularity of CISC microprocessors which were implemented by the manufacturers in calculators, video games, stereos, etc; RISC architecture was overshadowed. According to modern concept dates RISC computers were particularly introduced in the 1980s<\/strong>.<\/p>\n

In this section, we will discuss the architecture, instruction set, pipelining, advantages and disadvantage of the RISC processors.<\/p>\n

Content: RISC Processor<\/h2>\n
    \n
  1. RISC Architecture<\/a><\/li>\n
  2. RISC Instruction Sets<\/a><\/li>\n
  3. Pipelining in RISC<\/a><\/li>\n
  4. Advantages and Disadvantages<\/a><\/li>\n
  5. Examples<\/a><\/li>\n
  6. Key Takeaways<\/a><\/li>\n<\/ol>\n

    <\/a><\/p>\n

    RISC Processor Architecture (Block diagram)<\/h2>\n

    RISC processor is implemented using the hardwired control unit<\/a>.<\/strong> The hardwired control unit produces control signals<\/strong> which regulate the working of processors hardware. RISC architecture emphasizes on using the registers<\/strong> rather than memory.<\/p>\n

    This is because the registers are the ‘fastest’ available memory source. The registers are physically small and are placed on the same chip where the ALU and the control unit are placed on the processor. The RISC instructions operate<\/strong> on the operands present in processor’s registers<\/strong>.<\/p>\n

    Below we have the block diagram for the RISC architecture.<\/p>\n

    \"RISC<\/p>\n

    Observe one thing here, we don\u2019t<\/strong> have the “microprogram control store” or the “control memory” like we have seen in the CISC architecture<\/a> in our previous content.<\/p>\n

    It is just because all instructions in RISC are simple and execute one instruction per cycle. So, here the instructions are hardwired <\/strong>and there is no need for control store. For each operation, we will have as defined hardwire. Making an instruction hardwired is making a function or operation in instruction permanent<\/strong> using connected circuits.
    \n    <\/a><\/p>\n

    RISC Instruction Sets<\/h3>\n

    RISC instructions are simple and are of fixed<\/strong> size. Each RISC instruction engages a single memory word<\/strong>. RISC instructions operate on processor registers only. The instructions that have arithmetic and logic operation should have their operand either in the processor register<\/strong> or should be given directly <\/b>in the instruction.<\/p>\n

    Like in both the instructions below we have the operands in registers<\/p>\n

    Add R2, R3<\/strong><\/p>\n

    Add R2, R3, R4<\/strong><\/p>\n

    The operand can be mentioned directly in the instruction as below:<\/p>\n

    \u00a0Add R2, 100<\/strong><\/p>\n

    But initially, at the start of execution<\/strong> of the program, all the operands<\/strong> are in memory<\/strong>. So, to access the memory operands, the RISC instruction set has Load<\/strong> and Store<\/strong> instruction.<\/p>\n

    The Load<\/strong> instruction loads the operand present in memory<\/strong> to the processor register<\/strong>. The load instruction is of the form:<\/p>\n

    Load destination, Source<\/em><\/strong><\/p>\n

    Example Load R2, A \/\/ <\/strong>memory to register<\/em><\/p>\n

    The load instruction above will load the operand present at memory location A<\/strong> to the processor register R2<\/strong>.<\/p>\n

    The Store instruction stores the operand back to the memory. Generally, the Store instruction is used to store the intermediate result or the final result in the memory. It is of the form:<\/p>\n

    Store source, destinatio<\/em>n<\/strong><\/p>\n

    Example Store R2, A \/\/ <\/strong>register to memory<\/em><\/p>\n

    The Store instruction above will store the content in register R2<\/strong> into the A <\/strong> a memory location.<\/p>\n

    You can observe that in the example of Load and Store instruction operand side of both instructions appears the same as R2, A. But, the source and destination order of Store instruction is reversed in Load instruction.<\/p>\n

    RISC instruction has simple addressing modes. Below we have a list of RISC instruction type addressing modes<\/a>. Let us discuss them one by one.<\/p>\n

    Immediate addressing mode:<\/strong> This addressing mode explicitly<\/strong> specifies the operand in the instruction. Like<\/p>\n

    Add R4, R2, #200<\/strong><\/p>\n

    The above instruction will add 200 to the content of R2 and store the result in R4.<\/p>\n

    Register addressing mode:<\/strong> This addressing mode describes the registers<\/strong> holding the operands.<\/p>\n

    Add R3, R3, R4<\/strong><\/p>\n

    The above instruction will add the content of register R4 to the content of register R3 and store the result in R3.<\/p>\n

    Absolute addressing mode:<\/strong> This addressing mode describes a name for a memory location<\/strong>\u00a0in the instruction. It is used to declare global variables in the program.<\/p>\n

    Integer A, B, SUM;<\/strong><\/p>\n

    This instruction will allocate memory to variable A, B, SUM.<\/p>\n

    Register Indirect addressing mode:<\/strong> This addressing mode describes the register which has the address of the actual operand<\/strong> in the instruction. It is similar to pointers<\/strong> in HLL.<\/p>\n

    Load R2, (R3)<\/strong><\/p>\n

    This instruction will load the register R2 with the content, whose address is mentioned in register R3.<\/p>\n

    Index addressing mode:<\/strong> This addressing mode provides a register<\/strong> in the instruction, to which when we add a constant<\/strong>, obtain the address of the actual operand. It is similar to the array<\/strong> of HLL.<\/p>\n

    Load R2, 4(R3)<\/strong><\/p>\n

    This instruction will load the register R2 with the content present at the location obtained by adding 4 to the content of register R3.
    \n    <\/a><\/p>\n

    Pipelining in RISC<\/h3>\n

    As we know the RISC instructions are simple and engage one word<\/strong> in the memory. Even the ‘location of operands’ within the’ word’ is the same for the different instructions. Among all the instruction the Load and Store are the operations that accesses memory operand.<\/p>\n

    Most of the RISC instructions are register to register.<\/strong> If we consider the arithmetic and logic instructions, then we have two stages as follow:<\/p>\n

    Instruction Fetch (IF):<\/strong> Fetching the instruction<\/p>\n

    Instruction Execute (IE):<\/strong> ALU operation with the register<\/p>\n

    If we are considering the Load and Store instruction i.e. register to memory or memory to register, then three stages are required as follow.<\/p>\n

    Instruction Fetch (IF):<\/strong> Fetching the instruction<\/p>\n

    Instruction Execute (IE):<\/strong> Calculate memory address<\/p>\n

    Memory Store (M):<\/strong> register to register operation or memory to memory operation<\/p>\n

    Now consider the following instruction:<\/p>\n

    A <- B + C<\/strong><\/p>\n

    Creating a RISC instruction set for the above instruction will be.<\/p>\n

    Load R1, B<\/strong><\/p>\n

    Load R2, C<\/strong><\/p>\n

    Add R3, R2, R1<\/strong><\/p>\n

    Store R3, C<\/strong><\/p>\n

    Now in the figure below, we can see how the above RISC instructions are pipelined. The pipelined instructions fasten the execution twice when compared to execution in sequence. The instruction execution stage of first instruction & instruction fetch stage of second instruction is performed parallelly.<\/p>\n

    Observing the figure we can see that the execute\/memory stage of second instruction has to stall<\/strong> till the first instruction memory stage completes. This is the case when we use the single port memory<\/strong> i.e. only one memory access can be done at a time.<\/p>\n

    \"RISC<\/p>\n

    The above stalling condition reduces the execution speed. To overcome this, we can use NOOP<\/strong> (No Operation) instruction which can be inserted in the instruction stream by the compiler or assembler.<\/p>\n

    \"RISC<\/p>\n

     <\/p>\n

    This would speed up the execution as all the stages are of equal duration. But, what if the execution stage is longer, as it ALU operation. In this case, the IE stage is divided in two parts IE1<\/sub> register reading and IE2<\/sub> ALU operation.
    \n    <\/a><\/p>\n

    Advantages and Disadvantages of RISC Processor<\/h3>\n

    Advantages of RISC\u00a0 Processor<\/h4>\n
      \n
    1. RISC instructions are simpler machine instruction<\/strong>.<\/li>\n
    2. RISC instructions are hardwired<\/strong> to fasten the execution.<\/li>\n
    3. There are very fewer<\/strong> instructions in s RISC instruction set.<\/li>\n
    4. RISC instruction has simple addressing modes.<\/li>\n
    5. RISC instruction executes faster<\/strong> because most of instruction operates<\/strong> on processor register<\/strong> and there is no need to access memory for each instruction.<\/li>\n
    6. It is easy to pipeline<\/strong> RISC instruction as all instruction is of fixed size and opcode and operand are located in the same position in the word.<\/li>\n
    7. RISC instructions execute one<\/strong> instruction per clock cycle<\/strong>.<\/li>\n<\/ol>\n

      \u00a0Disadvantages of RISC Processor<\/h4>\n
        \n
      1. RISC instruction size is reduced but more instructions are required to perform an operation when compared with CISC. So, we can say that the length of the program is increased.<\/li>\n
      2. The machine instructions are hardwired<\/strong> in RISC so, it would cost<\/strong> if any instruction needs modification.<\/li>\n
      3. It finds is difficulty<\/strong> in processing complex instruction and complex addressing mode<\/strong>.<\/li>\n
      4. RISC instructions do not allow direct<\/strong> memory to memory transfer, it requires Load and Store instructions to do so.<\/li>\n<\/ol>\n

        <\/a><\/p>\n

        Examples of RISC processors<\/h3>\n

        MIPS, SPARC, IBM POWER instruction set, Alpha, RISC-V, ARM architecture.
        \n        <\/a><\/p>\n

        \n

        Key Takeaways<\/h3>\n
          \n
        • RISC instructions are simple<\/strong> and engages one word<\/strong> in memory.<\/li>\n
        • RISC instructions are of fixed size<\/strong>, the opcode and the operands in the instruction are located in the same position within a word in different instructions.<\/li>\n
        • One instruction in RISC architecture executes in one clock cycle<\/strong>.<\/li>\n
        • The instruction size is reduced but, it has increased<\/strong> the program length.<\/strong><\/li>\n
        • The pipelining<\/strong> of RISC instruction is easier.<\/li>\n
        • The machine instructions in RISC architecture are hardwired<\/strong>.<\/li>\n
        • RISC instruction operates only on register operands<\/strong>.<\/li>\n
        • RISC instruction executes faster<\/strong> as registers are placed in the processor chip which is faster available memory resource.<\/li>\n
        • RISC instruction performs memory to memory<\/strong> transfer via Load<\/strong> and Store<\/strong> instruction.<\/li>\n<\/ul>\n<\/div>\n

          This is all about the RISC processor and its instruction set architecture. RISC architecture is now used worldwide in cellular telephones, computer tables and even supercomputers.<\/p>\n","protected":false},"excerpt":{"rendered":"

          RISC is an abbreviation of Reduced Instruction Set Computer. RISC processor has ‘instruction sets’ that are simple and have simple ‘addressing modes’. A RISC style instruction engages “one word” in memory. Execution of the RISC instructions are faster and take one clock cycle per instruction. Although the forerunners of RISC computers were seen in 1960. […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"categories":[3],"tags":[],"class_list":{"0":"post-477","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-computer-architecture","7":"entry"},"yoast_head":"\nWhat is RISC Processor? Architecture, Instruction Sets, Pipelining, Examples, Advantages & Disadvantages - Binary Terms<\/title>\n<meta name=\"description\" content=\"RISC is an abbreviation of Reduced Instruction Set Computer. RISC processor are faster and take fewer clock cycles per instruction as compared to the CISC processors.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/binaryterms.com\/risc-processor.html\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"What is RISC Processor? Architecture, Instruction Sets, Pipelining, Examples, Advantages & Disadvantages - Binary Terms\" \/>\n<meta property=\"og:description\" content=\"RISC is an abbreviation of Reduced Instruction Set Computer. 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