{"id":326,"date":"2019-09-11T17:29:36","date_gmt":"2019-09-11T11:59:36","guid":{"rendered":"https:\/\/binaryterms.com\/?p=326"},"modified":"2021-01-18T13:04:38","modified_gmt":"2021-01-18T07:34:38","slug":"vector-processing","status":"publish","type":"post","link":"https:\/\/binaryterms.com\/vector-processing.html","title":{"rendered":"Vector Processing"},"content":{"rendered":"

Vector processing<\/strong> performs the arithmetic operation on the large array of integers or floating-point number. Vector processing operates on all the elements of the array in parallel providing each pass is independent of the other.<\/p>\n

Vector processing avoids the overhead<\/strong> of the loop control mechanism that occurs in general-purpose computers.<\/p>\n

In this section, we will have a brief introduction on vector processing, its characteristics, about vector instructions and how the performance of the vector processing can be enhanced? So lets us start.<\/p>\n

Content: Vector Processing in Computer Architecture<\/h2>\n
    \n
  1. Introduction<\/a><\/li>\n
  2. Characteristics<\/a><\/li>\n
  3. Vector Instruction<\/a><\/li>\n
  4. Improving Performance<\/a><\/li>\n
  5. Key Takeaways<\/a><\/li>\n<\/ol>\n

    <\/a><\/p>\n

    Introduction<\/h3>\n

    We need computers that can solve mathematical problems for us which include, arithmetic operations on the large arrays of integers or floating-point numbers quickly. The general-purpose computer would use loops to operate on an array of integers or floating-point numbers. But, for large array using loop would cause overhead to the processor.<\/p>\n

    To avoid the overhead of processing loops and fasten the computation, some kind of parallelism must be introduced. Vector processing<\/strong> operates on the entire array in just one operation i.e. it operates on elements of the array in parallel<\/strong>. But, vector processing is possible only if the operations performed in parallel are independent<\/strong>.<\/p>\n

    Look at the figure below, and compare the vector processing with the general computer processing, you will notice the difference. Below, instructions in both the blocks are set to add two arrays and store the result in the third array. Vector processing adds both the array in parallel by avoiding the use of the loop.<\/p>\n

    \"Vector<\/p>\n

    Operating on multiple data in just one instruction is also called Single Instruction Multiple Data<\/strong> (SIMD) or they are also termed as Vector instructions<\/strong>. Now, the data for vector instruction are stored in vector registers<\/strong>.<\/p>\n

    Each vector register is capable of storing several data elements at a time. These several data elements in a vector register is termed as a vector operand<\/strong>. So, if there are n number of elements in a vector operand then n is the length of the vector<\/strong>.<\/p>\n

    Supercomputers were evolved to deal with billions of floating-point operations\/second. Supercomputer optimizes numerical computations (vector computations).<\/p>\n

    But, along with vector processing supercomputers are also capable of doing scalar processing. Later, Array processor<\/strong> was introduced which particularly deals with vector processing, they do not indulge in scalar processing.
    \n    <\/a><\/p>\n

    Characteristics of Vector Processing<\/h2>\n

    Each element of the vector operand is a scalar quantity<\/strong> which can either be an integer, floating-point number, logical value or a character. Below we have classified the vector instructions in four types.<\/p>\n

    Here, V is representing the vector operands and S represents the scalar operands. In the figure below, O1 and O2 are the unary operations and O3 and O4 are the binary operations.
    \n\"Vector<\/p>\n

    Most of the vector instructions are pipelined<\/strong> as vector instruction performs the same operation on the different data sets repeatedly. Now, the pipelining has start-up delay, so longer vectors would perform better here.<\/p>\n

    The pipelined vector processors can be classified into two types based on from where the operand is being fetched<\/strong> for vector processing. The two architectural classifications are Memory-to-Memory and Register-to-Register.<\/p>\n

    In Memory-to-Memory<\/strong> vector processor the operands for instruction, the intermediate result and the final result all these are retrieved from the main memory<\/strong>. TI-ASC, CDC STAR-100, and Cyber-205 use memory-to-memory format for vector instructions.<\/p>\n

    In Register-to-Register<\/strong> vector processor the source operands for instruction, the intermediate result, and the final result all are retrieved from vector or scalar registers<\/strong>. Cray-1 and Fujitsu VP-200 use register-to-register format for vector instructions.
    \n    <\/a><\/p>\n

    Vector Instruction<\/h3>\n

    A vector instruction has the following fields:<\/p>\n

    1. Operation Code<\/h4>\n

    Operation code indicates the operation that<\/b>\u00a0has to be performed in the given instruction. It decides the functional unit for the specified operation or reconfigures the multifunction unit.<\/p>\n

    2. Base Address<\/h4>\n

    Base address field refers to the memory location<\/strong> from where the operands are to be fetched or to where the result has to be stored. The base address is found in the memory reference instructions. In the vector instruction, the operand and the result both are stored in the vector registers. Here, the base address<\/strong> refers to the designated vector register<\/strong>.<\/p>\n

    3. Address Increment<\/h4>\n

    A vector operand has several data elements and address increment specifies the address of the next element in the operand<\/strong>. Some computer stores the data element consecutively in main memory for which the increment is always 1. But, some computers that do not store the data elements consecutively requires the variable address increment.<\/p>\n

    4. Address Offset<\/h4>\n

    Address Offset is always specified related to the base address. The effective memory address <\/strong>is calculated using the address offset.<\/p>\n

    5. Vector Length<\/h4>\n

    Vector length specifies the number of elements in a vector operand<\/strong>. It identifies the termination<\/strong> of a vector instruction.
    \n    <\/a><\/p>\n

    Improving Performance<\/h3>\n

    In vector processing, we come across two overheads setup time and flushing time. When the vector processing is pipelined, the time required to route the vector operands<\/em> to the functional unit<\/em> is called Set up time<\/strong>. Flushing time<\/strong> is a time duration<\/em> that a vector instruction takes right from its decoding<\/em> until its first result is out<\/em> from the pipeline.<\/p>\n

    The vector length also affects the efficiency of processing as the longer vector length would cause overhead of subdividing the long vector for processing.<\/p>\n

    For obtaining the better performance the optimized object code must be produced in order to utilize pipeline resources to its maximum.<\/p>\n

    1. Improving the vector instruction<\/h4>\n

    We can improve the vector instruction by reducing the memory access, and maximize resource utilization.<\/p>\n

    2. Integrate the scalar instruction<\/h4>\n

    The scalar instruction of the same type must be integrated as a batch. As it will reduce the overhead of reconfiguring the pipeline again and again.<\/p>\n

    3. Algorithm<\/h4>\n

    Choose the algorithm that would work faster for vector pipelined processing.<\/p>\n

    4. Vectorizing Compiler<\/h4>\n

    A vectorizing compiler must regenerate the parallelism by using the higher-level programming language. In advance programming, the four-stage are identified in the development of the parallelism. Those are<\/p>\n