{"id":"https://openalex.org/W2124777811","doi":"https://doi.org/10.1109/iscas.2001.922099","title":"Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint","display_name":"Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint","publication_year":2002,"publication_date":"2002-11-13","ids":{"openalex":"https://openalex.org/W2124777811","doi":"https://doi.org/10.1109/iscas.2001.922099","mag":"2124777811"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2001.922099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2001.922099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103551595","display_name":"Po-Xun Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Po-Xun Chiu","raw_affiliation_strings":["Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102910503","display_name":"Yu\u2010Chung Lin","orcid":"https://orcid.org/0000-0003-1176-8915"},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Chung Lin","raw_affiliation_strings":["Department of Electronic Engineering, Chung Yuan Christian University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Chung Yuan Christian University, Taiwan","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101647524","display_name":"Yi\u2010Ling Hsieh","orcid":"https://orcid.org/0009-0001-4206-4526"},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Ling Hsieh","raw_affiliation_strings":["Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan","institution_ids":["https://openalex.org/I151221077"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108416600","display_name":"Tsai\u2010Ming Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I151221077","display_name":"Chung Yuan Christian University","ror":"https://ror.org/02w8ws377","country_code":"TW","type":"education","lineage":["https://openalex.org/I151221077"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsai-Ming Hsieh","raw_affiliation_strings":["Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Information and Computer Engineering, Chung Yuan Christian University, Taiwan","institution_ids":["https://openalex.org/I151221077"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103551595"],"corresponding_institution_ids":["https://openalex.org/I151221077"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19910642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"519","last_page":"522"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.7755633592605591},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7709804773330688},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7140011787414551},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6922118067741394},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.6344900131225586},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5793483257293701},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.5786411762237549},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.524990439414978},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4407412111759186},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39150795340538025},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3374335765838623},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.32755064964294434},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23817086219787598},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12791481614112854},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06476232409477234}],"concepts":[{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.7755633592605591},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7709804773330688},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7140011787414551},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6922118067741394},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.6344900131225586},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5793483257293701},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.5786411762237549},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.524990439414978},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4407412111759186},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39150795340538025},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3374335765838623},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.32755064964294434},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23817086219787598},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12791481614112854},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06476232409477234},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2001.922099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2001.922099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1806428288","https://openalex.org/W2010867627","https://openalex.org/W2055771903","https://openalex.org/W2058451007","https://openalex.org/W2079170559","https://openalex.org/W2116778055","https://openalex.org/W4231703706","https://openalex.org/W4253596588","https://openalex.org/W4254844210","https://openalex.org/W6638218184"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W3015599398","https://openalex.org/W2792778858","https://openalex.org/W2188730438","https://openalex.org/W2367816239","https://openalex.org/W1875529755","https://openalex.org/W1997308464","https://openalex.org/W2123314372","https://openalex.org/W2114992783"],"abstract_inverted_index":{"In":[0,60],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,21],"low":[6],"power":[7,36,48,68],"driven":[8],"re-synthesis":[9],"algorithm":[10,63],"for":[11],"LUT-based":[12],"heterogeneous":[13],"FPGA":[14],"under":[15],"delay":[16,22,41,72],"constraint.":[17],"We":[18],"start":[19],"with":[20],"optimal":[23],"solution":[24,29,54],"by":[25,58],"using":[26],"HeteroMap.":[27],"The":[28],"is":[30,42,74],"then":[31],"processed":[32],"to":[33],"reduce":[34,66],"the":[35,39,51,67,71],"consumption":[37,49,69],"and":[38],"circuit":[40],"held.":[43],"Experimental":[44],"results":[45],"show":[46],"that":[47],"of":[50],"original":[52],"mapping":[53],"has":[55],"been":[56],"reduced":[57],"15.02%.":[59],"addition,":[61],"our":[62],"can":[64],"further":[65],"when":[70],"constraint":[73],"relaxed.":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}