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Surv."],"published-print":{"date-parts":[[2022,1,31]]},"abstract":"<jats:p>Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this article, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.<\/jats:p>","DOI":"10.1145\/3510578","type":"journal-article","created":{"date-parts":[[2022,1,28]],"date-time":"2022-01-28T20:51:35Z","timestamp":1643403095000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":62,"title":["A Survey on Assertion-based Hardware Verification"],"prefix":"10.1145","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0761-6169","authenticated-orcid":false,"given":"Hasini","family":"Witharana","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, Florida, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8322-156X","authenticated-orcid":false,"given":"Yangdi","family":"Lyu","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology, Guangzhou, Guangdong, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6940-3057","authenticated-orcid":false,"given":"Subodha","family":"Charles","sequence":"additional","affiliation":[{"name":"University of Moratuwa, Moratuwa, Sri Lanka"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3653-6221","authenticated-orcid":false,"given":"Prabhat","family":"Mishra","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Florida, USA"}]}],"member":"320","published-online":{"date-parts":[[2022,9,9]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"Institute of Electrical and Electronics Engineers (IEEE). 2010. 1850-2010 - IEEE Standard for Property Specification Language (PSL). https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?arnumber=5446004."},{"key":"e_1_3_1_3_2","unstructured":"Institute of Electrical and Electronics Engineers (IEEE). 2012. 1800-2012 - IEEE Standard for SystemVerilog\u2013Unified Hardware Design Specification and Verification Language. https:\/\/webstore.ansi.org\/standards\/ieee\/ieee18002012"},{"key":"e_1_3_1_4_2","unstructured":"Open Verification Library (OVL) Working Group. 2014. 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