{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:49:00Z","timestamp":1750308540033,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,12,2]],"date-time":"2015-12-02T00:00:00Z","timestamp":1449014400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,12,2]]},"abstract":"<jats:p>\n            The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch\n            <jats:italic>M<\/jats:italic>\n            and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of\n            <jats:italic>M<\/jats:italic>\n            = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.\n          <\/jats:p>","DOI":"10.1145\/2770872","type":"journal-article","created":{"date-parts":[[2015,12,4]],"date-time":"2015-12-04T13:43:07Z","timestamp":1449236587000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs"],"prefix":"10.1145","volume":"21","author":[{"given":"Chien-Chih","family":"Huang","sequence":"first","affiliation":[{"name":"National Central University and Industrial Technology Research Institute, Taoyuan, Taiwan"}]},{"given":"Chin-Long","family":"Wey","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Jwu-E","family":"Chen","sequence":"additional","affiliation":[{"name":"National Central University, Taoyuan, Taiwan"}]},{"given":"Pei-Wen","family":"Luo","sequence":"additional","affiliation":[{"name":"Industrial Technology Research Institute, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2015,12,2]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"M. Burns and G. W. Roberts. 2001. An Introduction to Mixed-Signal IC Test and Measurement. Oxford University Press.  M. Burns and G. W. Roberts. 2001. An Introduction to Mixed-Signal IC Test and Measurement. Oxford University Press."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035587"},{"volume-title":"Proceedings of the 17th International Conference on Mixed Design of Integrated Circuits and Systems. 300--305","author":"Haenzsche S.","key":"e_1_2_1_3_1","unstructured":"S. Haenzsche , S. Henker , and R. Schuffny . 2010. Modeling of capacitor mismatch and nonlinearity effects in charge redistribution SAR ADCs . In Proceedings of the 17th International Conference on Mixed Design of Integrated Circuits and Systems. 300--305 . S. Haenzsche, S. Henker, and R. Schuffny. 2010. Modeling of capacitor mismatch and nonlinearity effects in charge redistribution SAR ADCs. In Proceedings of the 17th International Conference on Mixed Design of Integrated Circuits and Systems. 300--305."},{"volume-title":"The Art of Analog Layout","author":"Hastings A.","key":"e_1_2_1_4_1","unstructured":"A. Hastings . 2000. The Art of Analog Layout . Prentice Hall , Upper Saddle River, NJ. A. Hastings. 2000. The Art of Analog Layout. Prentice Hall, Upper Saddle River, NJ."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2534394"},{"key":"e_1_2_1_6_1","unstructured":"D. Johns and K. Martin. 1997. Analog Integrated Circuit Design. J. Wiley & Sons.  D. Johns and K. Martin. 1997. Analog Integrated Circuit Design. J. Wiley & Sons."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429519"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2323217"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226457"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593179"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024847"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2204993"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. 772--775","author":"Liu J.","key":"e_1_2_1_13_1","unstructured":"J. Liu , S. Dong , X. Hong , Y. Wang , O. He , and S. Goto . 2008. Symmetry constraint based on mismatch analysis for analog layout in SOI technology . In Proceedings of the Asia and South Pacific Design Automation Conference. 772--775 . J. Liu, S. Dong, X. Hong, Y. Wang, O. He, and S. Goto. 2008. Symmetry constraint based on mismatch analysis for analog layout in SOI technology. In Proceedings of the Asia and South Pacific Design Automation Conference. 772--775."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278684"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E94.A.352"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006139"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.284714"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. 576--580","author":"Sayed D.","key":"e_1_2_1_18_1","unstructured":"D. Sayed and M. Dessouky . 2002 Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio . In Proceedings of the Conference on Design, Automation and Test in Europe. 576--580 . D. Sayed and M. Dessouky. 2002 Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio. In Proceedings of the Conference on Design, Automation and Test in Europe. 576--580."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884403"},{"volume-title":"Proceedings of IEEE ICECS. 642--645","author":"Zhu Y.","key":"e_1_2_1_20_1","unstructured":"Y. Zhu , U-F. Chio , H.-G. Wei , S.-W. Sin , U. Seng-Pan , and R. P. Martins . 2008. A power-efficient capacitor structure for high-speed charge recycling SAR ADCs . In Proceedings of IEEE ICECS. 642--645 . Y. Zhu, U-F. Chio, H.-G. Wei, S.-W. Sin, U. Seng-Pan, and R. P. Martins. 2008. A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. In Proceedings of IEEE ICECS. 642--645."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2770872","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2770872","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T18:56:12Z","timestamp":1750272972000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2770872"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,2]]},"references-count":20,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,12,2]]}},"alternative-id":["10.1145\/2770872"],"URL":"https:\/\/doi.org\/10.1145\/2770872","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2015,12,2]]},"assertion":[{"value":"2014-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-12-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}