{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:56:23Z","timestamp":1771700183649,"version":"3.50.1"},"reference-count":33,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2022,5,26]],"date-time":"2022-05-26T00:00:00Z","timestamp":1653523200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Expert Systems"],"published-print":{"date-parts":[[2022,12]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>The reconfigurable capability of static random\u2010access memory (SRAM) field programmable gate array (FPGA) can be used for its fault self\u2010repair method. As a machine learning method, the genetic algorithm (GA) is an FPGA fault repair method that can be automatically executed on\u2010orbit without any ground support. However, the GA\u2010based fault repair method has disadvantages, such as the dependency on processors, the knowledge requirement for user designs in FPGAs, and the small size of repaired circuits. To address these issues, this paper presents a comprehensive analysis of the FPGA bitstream in the aerospace industry. An accurate on\u2010orbit fault location can be identified by bitstream copying and exhaustive test and the executed area of the GA can be reduced to one tile. In addition, the probability function of the algorithm is optimized, which converts floating\u2010point operations into integer arithmetic operations that are easily implemented in FPGAs without processors. The method is outstanding compared with existing ones, considering: (1) The size of repaired circuits is hundreds of times larger than those from other methods. (2) Its implementations are totally up to FPGAs' own logic, with no requirement for processors. (3) There is no knowledge requirement for user design. (4) It reaches the leading level with a success rate of 81%\u201393%. The method has been verified by various applications in XC7VX330T, which demonstrates its engineering practicability.<\/jats:p>","DOI":"10.1111\/exsy.13039","type":"journal-article","created":{"date-parts":[[2022,5,26]],"date-time":"2022-05-26T16:34:37Z","timestamp":1653582877000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["A genetic algorithm\u2010based on\u2010orbit self\u2010repair implementation for <scp>SRAM FPGAs<\/scp>"],"prefix":"10.1111","volume":"39","author":[{"given":"Fan","family":"Zhang","sequence":"first","affiliation":[{"name":"College of Aerospace Science and Engineering National University of Defense Technology  Changsha China"},{"name":"Department of FPGA Design Beijing Microelectronics Technology Institute  Beijing China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5711-7977","authenticated-orcid":false,"given":"Chenguang","family":"Guo","sequence":"additional","affiliation":[{"name":"School of Electronics and Information Northwestern Polytechnical University  Shaanxi China"}]},{"given":"Shifeng","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Aerospace Science and Engineering National University of Defense Technology  Changsha China"}]},{"given":"Qinqin","family":"Zeng","sequence":"additional","affiliation":[{"name":"Sci\u2010Tech Management Department China Construction Science &amp; Technology Group Co., Ltd.  Beijing China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4578-9925","authenticated-orcid":false,"given":"Tri Gia","family":"Nguyen","sequence":"additional","affiliation":[{"name":"Information Technology FPT University  Danang Vietnam"}]}],"member":"311","published-online":{"date-parts":[[2022,5,26]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2018.2828201"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2925932"},{"issue":"2","key":"e_1_2_9_4_1","first-page":"2","article-title":"Seu sensitivity and large spacing tmr efficiency of kintex\u20107 and virtex\u20107 fpgas","volume":"65","author":"Cai C.","year":"2022","journal-title":"Sciece China: Information Sciences"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11767-014-3168-9"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IDT52577.2021.9497584"},{"key":"e_1_2_9_7_1","doi-asserted-by":"publisher","DOI":"10.5120\/cae2016652148"},{"key":"e_1_2_9_8_1","volume-title":"Fpga accelerator architecture for q\u2010learning and its applications in space exploration rovers","author":"Gankidi P. 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