{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:54:14Z","timestamp":1730303654703,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,4]]},"DOI":"10.1109\/vts.2008.31","type":"proceedings-article","created":{"date-parts":[[2008,5,5]],"date-time":"2008-05-05T16:30:16Z","timestamp":1210005016000},"page":"119-124","source":"Crossref","is-referenced-by-count":8,"title":["Full Open Defects in Nanometric CMOS"],"prefix":"10.1109","author":[{"given":"Daniel","family":"Arumi","sequence":"first","affiliation":[]},{"given":"Rosa","family":"Rodriguez-Montanes","sequence":"additional","affiliation":[]},{"given":"Joan","family":"Figueras","sequence":"additional","affiliation":[]},{"given":"Stefan","family":"Eichenberger","sequence":"additional","affiliation":[]},{"given":"Camelia","family":"Hora","sequence":"additional","affiliation":[]},{"given":"Bram","family":"Kruseman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261021"},{"year":"0","key":"22"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843859"},{"key":"23","first-page":"201","volume":"299","author":"cao","year":"2000","journal-title":"New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907255"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519522"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741618"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527999"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/43.372374"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904442"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1049\/el:20072117"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519522"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.28"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19860106"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033788"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/16.930653"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041766"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.811326"},{"year":"0","key":"5"},{"key":"4","first-page":"443","article-title":"probability analysis for cmos floating gate faults","author":"sue","year":"1994","journal-title":"European Design and Test Conference"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/16.285029"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1992.200622"}],"event":{"name":"2008 IEEE VLSI Test Symposium (VTS '08)","start":{"date-parts":[[2008,4,27]]},"location":"San Diego, CA","end":{"date-parts":[[2008,5,1]]}},"container-title":["26th IEEE VLSI Test Symposium (vts 2008)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4511672\/4511673\/04511708.pdf?arnumber=4511708","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,22]],"date-time":"2019-08-22T19:49:51Z","timestamp":1566503391000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4511708\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/vts.2008.31","relation":{},"subject":[],"published":{"date-parts":[[2008,4]]}}}