{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:55:09Z","timestamp":1747810509245,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,10]]},"DOI":"10.1109\/test.2006.297695","type":"proceedings-article","created":{"date-parts":[[2007,2,12]],"date-time":"2007-02-12T16:16:43Z","timestamp":1171297003000},"page":"1-8","source":"Crossref","is-referenced-by-count":37,"title":["BIST Power Reduction Using Scan-Chain Disable in the Cell Processor"],"prefix":"10.1109","author":[{"given":"Christian","family":"Zoellin","sequence":"first","affiliation":[]},{"given":"Hans-joachim","family":"Wunderlich","sequence":"additional","affiliation":[]},{"given":"Nicolas","family":"Maeding","sequence":"additional","affiliation":[]},{"given":"Jens","family":"Leenstra","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968648"},{"key":"ref30","first-page":"442","article-title":"X-masking during logic bist and its impact on defect coverage","author":"tang","year":"2004","journal-title":"Proc IEEE International Test Conference (ITC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894297"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.96"},{"key":"ref12","first-page":"51","article-title":"Minimizing power dissipation in scan circuits during test application","author":"chakravarty","year":"1994","journal-title":"1994 Int Workshop on Low-Power Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.736572"},{"key":"ref14","first-page":"62","article-title":"Design of routing-constrained low power scan chains","author":"bonhomme","year":"2004","journal-title":"2004 Design Automation and Test in Europe Conference and Exposition (DATE 2004)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894260"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639699"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805617"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843823"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923456"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207808"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805650"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/988952.988974"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1998.670910"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766696"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2004.1347857"},{"key":"ref2","first-page":"200","article-title":"Self-testing of multichip logic modules","author":"bardell","year":"1982","journal-title":"Proceedings International Test Conference 1982"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008331029249"},{"key":"ref1","first-page":"19","article-title":"Random patterns within a structured sequential logic design","author":"williams","year":"1977","journal-title":"Dig Semiconductor Test Symp"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923454"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493930"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583967"},{"key":"ref24","first-page":"165","article-title":"A logic design structure for LSI testability","volume":"2","author":"eichelberger","year":"1978","journal-title":"Journal of Design Automatica and Fault-Tolerant Computing"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493905"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1147\/rd.342.0406"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.33"}],"event":{"name":"2006 IEEE International Test Conference","start":{"date-parts":[[2006,10,22]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2006,10,27]]}},"container-title":["2006 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4079296\/4042774\/04079373.pdf?arnumber=4079373","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T14:50:19Z","timestamp":1489589419000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4079373\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/test.2006.297695","relation":{},"ISSN":["1089-3539"],"issn-type":[{"type":"print","value":"1089-3539"}],"subject":[],"published":{"date-parts":[[2006,10]]}}}