{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,19]],"date-time":"2025-10-19T15:19:57Z","timestamp":1760887197801,"version":"3.28.0"},"reference-count":17,"publisher":"Int. Test Conference","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/test.2000.894274","type":"proceedings-article","created":{"date-parts":[[2002,11,8]],"date-time":"2002-11-08T02:03:12Z","timestamp":1036720992000},"page":"778-784","source":"Crossref","is-referenced-by-count":83,"title":["A mixed mode BIST scheme based on reseeding of folding counters"],"prefix":"10.1109","author":[{"given":"S.","family":"Hellebrand","sequence":"first","affiliation":[]},{"family":"Hua-Guo Liang","sequence":"additional","affiliation":[]},{"given":"H.-J.","family":"Wunderlich","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.479997"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1023\/A:1008294125692","article-title":"Mixed-Mode BIST Using Embedded Processors","volume":"12","author":"hellebrand","year":"1998","journal-title":"Journal of Electronic Testing Theory and Applications (JETTA)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.545970"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639636"},{"key":"ref14","first-page":"237","article-title":"LFSR-Coded Test Patterns for Scan Designs","author":"koenemann","year":"1991","journal-title":"Proc Eur Test Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676477"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556959"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569803"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766642"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727020"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529913"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.1999.803819"},{"key":"ref7","first-page":"27","article-title":"LFSR based Deterministic and Pseudo-Random Test Pattern Generator Structures","author":"dufaza","year":"1991","journal-title":"Proc Eur Test Conf"},{"key":"ref2","article-title":"Accelerated ATPG and fault grading via testability analysis","author":"brglez","year":"1985","journal-title":"Proc IEEE Int Symp on Circuits and Systems"},{"journal-title":"Digital Systems Testing and Testable Design","year":"1990","author":"abramovici","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.364534"}],"event":{"name":"International Test Conference 2000","acronym":"TEST-00","location":"Atlantic City, NJ, USA"},"container-title":["Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7183\/19342\/00894274.pdf?arnumber=894274","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T13:57:12Z","timestamp":1497535032000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/894274\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/test.2000.894274","relation":{},"subject":[]}}