{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,5]],"date-time":"2025-07-05T04:46:10Z","timestamp":1751690770434,"version":"3.28.0"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2003,11,1]],"date-time":"2003-11-01T00:00:00Z","timestamp":1067644800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2003,11,1]],"date-time":"2003-11-01T00:00:00Z","timestamp":1067644800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2003,11,1]],"date-time":"2003-11-01T00:00:00Z","timestamp":1067644800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. II"],"published-print":{"date-parts":[[2003,11]]},"DOI":"10.1109\/tcsii.2003.819121","type":"journal-article","created":{"date-parts":[[2003,11,20]],"date-time":"2003-11-20T23:29:22Z","timestamp":1069370962000},"page":"879-886","source":"Crossref","is-referenced-by-count":33,"title":["Analysis of PLL clock jitter in high-speed serial links"],"prefix":"10.1109","volume":"50","author":[{"given":"P.K.","family":"Hanumolu","sequence":"first","affiliation":[{"name":"Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA"}]},{"given":"B.","family":"Casper","sequence":"additional","affiliation":[]},{"given":"R.","family":"Mooney","sequence":"additional","affiliation":[]},{"family":"Gu-Yeon Wei","sequence":"additional","affiliation":[]},{"family":"Un-Ku Moon","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.50307"},{"journal-title":"ADS Design Guides","article-title":"Advanced design systems","year":"2000","key":"ref12"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/82.782040"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"2015","DOI":"10.1109\/4.545825","article-title":"A $0.8\\ \\mu$ m CMOS 2.5 Gb\/s oversampling receiver and transmitter for serial links","volume":"31","author":"yang","year":"1996","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759289"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.658625"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2002.802353"},{"key":"ref10","first-page":"252","article-title":"A 90 mW 4 Gb\/s equalized I\/O circuit with input offset cancelation","author":"lee","year":"2000","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref21","first-page":"38","article-title":"Numerical modeling of PLL jitter and the impact of its nonwhite spectrum on the SNR of sampled signals","author":"da dalt","year":"2001","journal-title":"Proc Southwest Symp Mixed-Signal Design"},{"key":"ref2","first-page":"76","article-title":"A 2.5&#x2013;10 Gb\/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization","author":"lee","year":"2003","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"78","article-title":"8 Gb\/s differential simultaneous bidirectional link with 4 mV 9 ps waveform capture diagnostic capability","author":"casper","year":"2003","journal-title":"ISSCC Dig Tech Papers"},{"journal-title":"Digital Communications","year":"2000","author":"proakis","key":"ref17"},{"journal-title":"Digital Communication","year":"1999","author":"lee","key":"ref16"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1997.585369"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.841504"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.165341"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.475714"},{"key":"ref9","first-page":"142","article-title":"A 700 Mbps\/pin CMOS signaling interface using current integrating receivers","author":"sidiropoulos","year":"1996","journal-title":"Proc VLSI Circuits Symp"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.760366"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015043"}],"container-title":["IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/82\/27926\/01246365.pdf?arnumber=1246365","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:30:47Z","timestamp":1729618247000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1246365\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,11]]},"references-count":22,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcsii.2003.819121","relation":{},"ISSN":["1057-7130","1558-125X"],"issn-type":[{"type":"print","value":"1057-7130"},{"type":"electronic","value":"1558-125X"}],"subject":[],"published":{"date-parts":[[2003,11]]}}}