{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,7]],"date-time":"2025-11-07T08:46:55Z","timestamp":1762505215904},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2007,2,1]],"date-time":"2007-02-01T00:00:00Z","timestamp":1170288000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2007,2]]},"DOI":"10.1109\/tcad.2006.887922","type":"journal-article","created":{"date-parts":[[2007,1,23]],"date-time":"2007-01-23T19:44:57Z","timestamp":1169581497000},"page":"230-239","source":"Crossref","is-referenced-by-count":45,"title":["Optimality Study of Logic Synthesis for LUT-Based FPGAs"],"prefix":"10.1109","volume":"26","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[]},{"given":"Kirill","family":"Minkovich","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","year":"0","journal-title":"Quartus 5 0"},{"key":"ref38","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref33","author":"sze","year":"2006","journal-title":"Multilevel optimization for VLSI circuit placement"},{"key":"ref32","author":"sentovitch","year":"1992","journal-title":"SIS A system for sequential circuit synthesis"},{"key":"ref31","first-page":"83","article-title":"technology mapping for table-look-up based field programmable gate arrays","author":"sawkar","year":"1992","journal-title":"Proc ACM\/SIGDA Workshop Field-Programmable Gate Arrays"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055184"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368658"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629758"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127675"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846365"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580040"},{"key":"ref40","year":"0","journal-title":"ISE Logic Design Tools 7 1i"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/233539.233540"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/FPGA.1995.241947","article-title":"simultaneous depth and area minimization in lut-based fpga mapping","author":"cong","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981083"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1109\/FPGA.1996.242541","article-title":"rasp: a general logic synthesis system for sram-based fpgas","author":"cong","year":"1996","journal-title":"Fourth International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159726"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/640020.640021"},{"key":"ref19","first-page":"748","article-title":"hermes: lut fpga technology mapping algorithm for area minimization with optimum depth","author":"dubrova","year":"2004","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref28","article-title":"on sub-optimality and scalability of logic synthesis tools","author":"markov","year":"2003","journal-title":"Proc Int Workshop Logic and Synthesis"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055177"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545669"},{"key":"ref3","first-page":"14","article-title":"heuristics for area minimization in lut based fpga technology mapping","author":"brown","year":"2004","journal-title":"Proc Int Workshop Logic and Synthesis"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1195099"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185333"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159704"},{"key":"ref8","article-title":"a decade of advances in fpga design automation","volume":"1","author":"chen","year":"2006","journal-title":"Foundations and Trends Electron Des Autom"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"key":"ref2","first-page":"427","article-title":"fpga technology mapping: a study of optimality","author":"brown","year":"2005","journal-title":"Proc Des Autom Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/54.156154"},{"key":"ref1","first-page":"383","article-title":"an integrated technology mapping environment","author":"brayton","year":"2005","journal-title":"Proc Int Workshop Logic and Synthesis"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1145\/127601.127670","article-title":"Chortle-crf: fast technology mapping for lookup table-based FPGAs","author":"francis","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981071"},{"key":"ref21","author":"garey","year":"1979","journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1145\/127601.127672","article-title":"Xmap: a technology mapper for table-lookup field-programmable gate arrays","author":"karplus","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref41","year":"0","journal-title":"UCLA Optimality Study Project"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055180"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597203"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/43\/4068913\/04068916.pdf?arnumber=4068916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:09Z","timestamp":1638218409000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4068916\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,2]]},"references-count":41,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2006.887922","relation":{},"ISSN":["0278-0070"],"issn-type":[{"value":"0278-0070","type":"print"}],"subject":[],"published":{"date-parts":[[2007,2]]}}}