{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,6]],"date-time":"2026-01-06T13:33:42Z","timestamp":1767706422160,"version":"3.40.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2010,3,1]],"date-time":"2010-03-01T00:00:00Z","timestamp":1267401600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/tc.2009.130","type":"journal-article","created":{"date-parts":[[2009,9,11]],"date-time":"2009-09-11T19:02:42Z","timestamp":1252695762000},"page":"332-344","source":"Crossref","is-referenced-by-count":8,"title":["Design and Analysis of On-Chip Networks for Large-Scale Cache Systems"],"prefix":"10.1109","volume":"59","author":[{"given":"Yuho","family":"Jin","sequence":"first","affiliation":[]},{"given":"Eun Jung","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Ki Hwan","family":"Yum","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","first-page":"248","article-title":"Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures","volume-title":"Proc. Int\u2019l Symp. Computer Architecture (ISCA)","author":"Agarwal"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2001.902687"},{"key":"ref4","first-page":"684","article-title":"Route Packets, Not Wires: On-Chip Interconnection Networks","volume-title":"Proc. Design Automation Conf. (DAC)","author":"Dally"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012731"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1044299"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.24"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2003.1207019"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854387"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253183"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253182"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250708"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183554"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903268"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310774"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264129"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/115953.115965"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1992.753324"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594676"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250681"},{"year":"2003","key":"ref27","article-title":"International Technology Roadmap for Semiconductors"},{"key":"ref28","first-page":"141","article-title":"Scalable Pipelined Interconnect for Distributed Endpoint Routing: The SGI SPIDER Chip","volume-title":"Proc. Hot Interconnect","author":"Galles"},{"key":"ref29","article-title":"Sim-alpha: A Validated, Execution-Driven Alpha 21264 Simulator","volume-title":"Technical Report TR-01-23, Dept. of Computer Sciences, The Univ. of Texas at Austin","author":"Desikan","year":"2001"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"journal-title":"Compaq Computer Corporation 2001","article-title":"Cacti 3.0: An Integrated Cache Timing, Power and Area Model","author":"Shivakumar","key":"ref31"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176258"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346209"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/5398795\/05235140.pdf?arnumber=5235140","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T04:59:36Z","timestamp":1742273976000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5235140\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":33,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.2009.130","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2010,3]]}}}