{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:21:09Z","timestamp":1730283669548,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,12]]},"DOI":"10.1109\/mtv.2006.10","type":"proceedings-article","created":{"date-parts":[[2007,5,30]],"date-time":"2007-05-30T14:14:00Z","timestamp":1180534440000},"page":"33-36","source":"Crossref","is-referenced-by-count":7,"title":["Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study"],"prefix":"10.1109","author":[{"given":"Heon-Mo","family":"Koo","sequence":"first","affiliation":[]},{"given":"Prabhat","family":"Mishra","sequence":"additional","affiliation":[]},{"given":"Jayanta","family":"Bhadra","sequence":"additional","affiliation":[]},{"given":"Magdy","family":"Abadir","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008388623771"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146997"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/54.895005"},{"journal-title":"Cadence SMV","year":"0","key":"ref13"},{"journal-title":"Freescale PowerPc e500 core family reference manual","year":"0","key":"ref14"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2002","author":"hennessy","key":"ref4"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1145\/318774.318939","article-title":"Using model checking to generate tests from requirements specifications","volume":"24","author":"gargantini","year":"1999","journal-title":"ACM SIGSOFT Software Engineering Notes"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379072"},{"key":"ref5","first-page":"580","article-title":"Automatic test pattern generation for pipelined processors","author":"iwashita","year":"1994","journal-title":"ICCAD"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127991"},{"key":"ref7","first-page":"1240","article-title":"Functional test generation using property decompositions for validation of pipelined processors","author":"koo","year":"2006","journal-title":"DATE"},{"journal-title":"Model checking","year":"1999","author":"clarke","key":"ref2"},{"key":"ref1","first-page":"185","article-title":"High-level test generation for design verification of pipelined microprocessors","author":"campenhout","year":"1999","journal-title":"DAC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268846"}],"event":{"name":"2006 IEEE International Workshop on Microprocessor Test and Verification","start":{"date-parts":[[2006,12,4]]},"location":"Austin, TX","end":{"date-parts":[[2006,12,5]]}},"container-title":["Seventh International Workshop on Microprocessor Test and Verification (MTV'06)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4197205\/4197206\/04197219.pdf?arnumber=4197219","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T15:22:14Z","timestamp":1580916134000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4197219\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/mtv.2006.10","relation":{},"subject":[],"published":{"date-parts":[[2006,12]]}}}