{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:40:52Z","timestamp":1761648052971,"version":"3.44.0"},"reference-count":48,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/micro.2012.11","type":"proceedings-article","created":{"date-parts":[[2013,4,11]],"date-time":"2013-04-11T17:05:08Z","timestamp":1365699908000},"page":"13-24","source":"Crossref","is-referenced-by-count":45,"title":["Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access"],"prefix":"10.1109","author":[{"given":"Niladrish","family":"Chatterjee","sequence":"first","affiliation":[]},{"given":"Manjunath","family":"Shevgoor","sequence":"additional","affiliation":[]},{"given":"Rajeev","family":"Balasubramonian","sequence":"additional","affiliation":[]},{"given":"Al","family":"Davis","sequence":"additional","affiliation":[]},{"given":"Zhen","family":"Fang","sequence":"additional","affiliation":[]},{"given":"Ramesh","family":"Illikkal","sequence":"additional","affiliation":[]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Memory Systems Cache","year":"2008","author":"jacob","key":"19"},{"key":"35","article-title":"MLP?aware heterogeneous main memory","author":"phadke","year":"2011","journal-title":"Proceedings of DATE"},{"journal-title":"Critical Words Cache Memory Exploiting Criticality Withing Primary Cache Miss Streams","year":"2008","author":"gieske","key":"17"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2007","author":"hennessy","key":"18"},{"key":"33","article-title":"Power?aware memory manage? ment for hybrid main memory","author":"park","year":"2011","journal-title":"Proceedings of ICNIT"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"},{"key":"34","article-title":"Hybrid memory cube (HMC)","author":"pawlowski","year":"2011","journal-title":"HOTCHIPS"},{"key":"16","article-title":"Synthesizing memory?level paral? lelism aware miniature clones for spec cpu2006 and implantbench workloads","author":"ganesan","year":"2010","journal-title":"Proc ISPA"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736045"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765953"},{"key":"14","doi-asserted-by":"crossref","first-page":"664","DOI":"10.1145\/1629911.1630086","article-title":"pdram: a hybrid pram and dram main memory system","author":"dhiman","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555372"},{"journal-title":"USIMM The Utah Simulated Memory Module","year":"2012","author":"chatterjee","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.73"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.100"},{"key":"43","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"journal-title":"Ten Reasons Why Oracle Databases Run Best on Vmware","year":"2007","key":"42"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2007.30"},{"key":"48","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"45","article-title":"BOOM: Enabling mobilememory based low?power server dimms","author":"yoon","year":"0","journal-title":"Proc ISCAS-2012"},{"key":"44","doi-asserted-by":"crossref","DOI":"10.1145\/1105734.1105748","article-title":"Dramsim: A memory?system simulator","author":"wang","year":"2005","journal-title":"SIGArch Computer Architecture News"},{"key":"47","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.27"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"journal-title":"UltraSPARC T1 A 32? Threaded CMP for Servers","year":"2006","author":"laudon","key":"22"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"24","article-title":"Efficiently enabling conventional block sizes for very large die?stacked dram caches","author":"loh andm hill","year":"2011","journal-title":"Proceedings of MICRO"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508269"},{"journal-title":"Micron Technology Inc","article-title":"Micron ddr3 sdram part mt41j256m8","year":"2006","key":"28"},{"journal-title":"Micron Technol? Ogy Inc","article-title":"Micron mobile lpddr2 part mt42l128m16d1","year":"2010","key":"29"},{"year":"0","key":"3"},{"year":"0","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815967"},{"year":"0","key":"1"},{"journal-title":"Micron Technology Inc","article-title":"Micron rldram 3 part mt44k32m18","year":"2011","key":"30"},{"year":"2011","key":"7"},{"year":"2008","key":"6"},{"key":"32","article-title":"A 1.2v 30nm 1.6gb\/s\/pin 4gb lpddr3 sdram with input skew calibration and enhanced control scheme","author":"park","year":"2012","journal-title":"Proceedings of ISSCC"},{"year":"2007","key":"5"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/1713254.1713276"},{"year":"0","key":"4"},{"journal-title":"BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors","article-title":"AMD inc","year":"0","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"}],"event":{"name":"2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2012,12,1]]},"location":"Vancouver, BC, Canada","end":{"date-parts":[[2012,12,5]]}},"container-title":["2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6490492\/6493591\/06493604.pdf?arnumber=6493604","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,25]],"date-time":"2025-08-25T20:18:39Z","timestamp":1756153119000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6493604\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/micro.2012.11","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}