{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:53:54Z","timestamp":1725630834041},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/iscas.2013.6572372","type":"proceedings-article","created":{"date-parts":[[2013,8,14]],"date-time":"2013-08-14T15:40:23Z","timestamp":1376494823000},"page":"2440-2443","source":"Crossref","is-referenced-by-count":2,"title":["A hybrid CBRAM\/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array"],"prefix":"10.1109","author":[{"given":"Santhosh","family":"Onkaraiah","sequence":"first","affiliation":[]},{"given":"Ogun","family":"Turkyilmaz","sequence":"additional","affiliation":[]},{"given":"Marina","family":"Reyboz","sequence":"additional","affiliation":[]},{"given":"Fabien","family":"Clermidy","sequence":"additional","affiliation":[]},{"given":"Elisa","family":"Vianello","sequence":"additional","affiliation":[]},{"given":"Jean-Michel","family":"Portal","sequence":"additional","affiliation":[]},{"given":"Christophe","family":"Muller","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177067"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311199"},{"key":"14","article-title":"A detailed power model for field-programmable gate arrays","author":"kara","year":"0","journal-title":"TODAES '05"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377675"},{"year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419328"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269271"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249359"},{"year":"0","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213680"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2013.6632872"},{"key":"5","article-title":"Conductive bridging memory development from single cells to 2mbit memory arrays","author":"symanczyk","year":"0","journal-title":"NVMTS '07"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796675"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2765491.2765510"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"}],"event":{"name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2013,5,19]]},"location":"Beijing","end":{"date-parts":[[2013,5,23]]}},"container-title":["2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6560459\/6571764\/06572372.pdf?arnumber=6572372","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T21:09:10Z","timestamp":1490216950000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6572372\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas.2013.6572372","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}