{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:36:21Z","timestamp":1761647781370,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/iscas.2010.5537694","type":"proceedings-article","created":{"date-parts":[[2010,8,9]],"date-time":"2010-08-09T22:13:20Z","timestamp":1281392000000},"page":"3893-3896","source":"Crossref","is-referenced-by-count":18,"title":["Error control integration scheme for reliable NoC"],"prefix":"10.1109","author":[{"given":"Qiaoyan","family":"Yu","sequence":"first","affiliation":[]},{"given":"Bo","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Yan","family":"Li","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Ampadu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.20"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.40"},{"key":"ref12","first-page":"1313","article-title":"Unequal error protection codes with two-level burst and bit error correcting capability","author":"namba","year":"1998","journal-title":"Proc DFT'98"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"journal-title":"NetWorks On Chips","year":"2007","author":"de micheli","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ITNG.2008.55"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2009.5270337"},{"key":"ref4","first-page":"13","article-title":"Survey of network-on-chip proposals","author":"salminen","year":"2008","journal-title":"White paper OCP-IP"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2003.1183347"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848816"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847907"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5035-1"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.104"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225959"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"2042","DOI":"10.1109\/TCSI.2009.2026679","article-title":"On hamming product codes with type-II hybrid ARQ for on-chip interconnects","volume":"56","author":"fu","year":"2009","journal-title":"IEEE Trans on Circuits and Syst I"}],"event":{"name":"2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010","start":{"date-parts":[[2010,5,30]]},"location":"Paris, France","end":{"date-parts":[[2010,6,2]]}},"container-title":["Proceedings of 2010 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5512009\/5536941\/05537694.pdf?arnumber=5537694","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T12:20:09Z","timestamp":1497874809000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5537694\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2010.5537694","relation":{},"subject":[],"published":{"date-parts":[[2010,5]]}}}