{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:15:50Z","timestamp":1729649750489,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/ipdpsw.2013.219","type":"proceedings-article","created":{"date-parts":[[2013,11,2]],"date-time":"2013-11-02T00:35:37Z","timestamp":1383352537000},"page":"931-937","source":"Crossref","is-referenced-by-count":2,"title":["Energy-Efficient Sparse Matrix Autotuning with CSX -- A Trade-off Study"],"prefix":"10.1109","author":[{"given":"Jan Christian","family":"Meyer","sequence":"first","affiliation":[]},{"given":"Juan Manuel","family":"Cebrian","sequence":"additional","affiliation":[]},{"given":"Lasse","family":"Natvig","sequence":"additional","affiliation":[]},{"given":"Vasileios","family":"Karakasis","sequence":"additional","affiliation":[]},{"given":"Dimitris","family":"Siakavaras","sequence":"additional","affiliation":[]},{"given":"Konstantinos","family":"Nikas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253774"},{"key":"22","first-page":"127","article-title":"Optimizing sparse matrix computations for register reuse in SPARSITY","author":"im","year":"2001","journal-title":"Proceedings of the International Conference on Computational Sciences-Part i"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454151"},{"journal-title":"The University of Florida sparse matrix collection","year":"2013","key":"23"},{"key":"18","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1145\/1577129.1577137","article-title":"Real time power estimation and thread scheduling via performance counters","volume":"37","author":"singh","year":"2009","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32606-6_4"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196115"},{"key":"16","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"sheng","year":"2009","journal-title":"42nd Annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2012.290"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253186"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"12","first-page":"148","article-title":"Drowsy caches: Simple techniques for reducing leakage power","author":"flautner","year":"2001","journal-title":"29th Annual International Symposium on Computer Architecture"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176251"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781138"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124723"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01721-6","article-title":"Computer Architecture Techniques for Power-Efficiency ser","volume":"3","author":"kaxiras","year":"2008","journal-title":"Synthesis Lectures on Computer Architecture Morgan & Claypool"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/40.888701"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903259"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.53"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995696"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349330"},{"key":"9","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"Proceedings of the international symposium on Low power electronics and design"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"}],"event":{"name":"2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","start":{"date-parts":[[2013,5,20]]},"location":"Cambridge, MA, USA","end":{"date-parts":[[2013,5,24]]}},"container-title":["2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6603430\/6650854\/06650975.pdf?arnumber=6650975","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,6]],"date-time":"2023-07-06T00:07:55Z","timestamp":1688602075000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6650975\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/ipdpsw.2013.219","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}