{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:08Z","timestamp":1759147568984,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/inis.2015.66","type":"proceedings-article","created":{"date-parts":[[2016,3,17]],"date-time":"2016-03-17T20:29:16Z","timestamp":1458246556000},"page":"112-117","source":"Crossref","is-referenced-by-count":3,"title":["Reconfigurable Concurrent VLSI (FPGA) Design Architecture of CRC-32 for High-Speed Data Communication"],"prefix":"10.1109","author":[{"given":"Jubin","family":"Mitra","sequence":"first","affiliation":[]},{"given":"Tapan K.","family":"Nayak","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810780"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/35.135787"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1966.264565"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1002\/9780470127896","author":"kilts","year":"2007","journal-title":"Advanced FPGA Design Architecture Implementation and Optimization"},{"journal-title":"White Paper no WP-01139–1 0","article-title":"Guaranteeing Silicon Performance with FPGA Timing Models","year":"2010","key":"ref14"},{"key":"ref15","article-title":"The gbt: A proposed architecture for multi-gb\/s data transmission in high energy physics","author":"moreira","year":"0","journal-title":"Published in Prague 2007"},{"journal-title":"Tech Rep","article-title":"Upgrade of the ALICE Readout & Trigger System","year":"2014","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008741"},{"article-title":"Catalogue of parametrised crc algorithms","year":"2010","author":"cook","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311885"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"764","DOI":"10.1109\/DATE.2004.1268972","article-title":"Cost-performance trade-offs in networks on chip: A simulation-based approach","volume":"2","author":"pestana","year":"2004","journal-title":"Design Automation and Test in Europe Conference and Exhibition 2004 Proceedings"},{"journal-title":"Tech Rep","article-title":"Quartus II Handbook Version 13.1","year":"2013","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2001.957433"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/30.370327"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344695"}],"event":{"name":"2015 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)","start":{"date-parts":[[2015,12,21]]},"location":"Indore, India","end":{"date-parts":[[2015,12,23]]}},"container-title":["2015 IEEE International Symposium on Nanoelectronic and Information Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7434373\/7434375\/07434408.pdf?arnumber=7434408","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,15]],"date-time":"2024-06-15T02:31:44Z","timestamp":1718418704000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7434408\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/inis.2015.66","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}