{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:19:16Z","timestamp":1730222356807,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/fpl.2012.6339212","type":"proceedings-article","created":{"date-parts":[[2012,10,26]],"date-time":"2012-10-26T21:47:45Z","timestamp":1351288065000},"page":"583-586","source":"Crossref","is-referenced-by-count":2,"title":["HCM: An abstraction layer for seamless programming of DPR FPGA"],"prefix":"10.1109","author":[{"given":"Yan","family":"Xu","sequence":"first","affiliation":[]},{"given":"Olivier","family":"Muller","sequence":"additional","affiliation":[]},{"given":"Pierre-Henri","family":"Horrein","sequence":"additional","affiliation":[]},{"given":"Frederic","family":"Petrot","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.73"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.6"},{"journal-title":"Soclib Website","year":"2010","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.888404"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005670"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.380"},{"journal-title":"BORPH An Operating System for FPGA-based Reconfigurable Computers","year":"2007","author":"so","key":"4"},{"key":"9","first-page":"965","article-title":"A parallel configuration model for reducing the run-time reconfiguration overhead","author":"qu","year":"0","journal-title":"Proc Conf Design Automation and Test in Europe 2006"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515777"},{"key":"11","first-page":"381","article-title":"A simulation tool for dynamically reconfigurable fieldprogrammable gate arrays","volume":"4","author":"stockwood","year":"1995","journal-title":"IEEE Trans VLSI Syst"},{"journal-title":"\"HCM Website and Source Repository \" [Online]","year":"0","key":"12"}],"event":{"name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2012,8,29]]},"location":"Oslo, Norway","end":{"date-parts":[[2012,8,31]]}},"container-title":["22nd International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6330714\/6339128\/06339212.pdf?arnumber=6339212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T01:35:13Z","timestamp":1490146513000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6339212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/fpl.2012.6339212","relation":{},"subject":[],"published":{"date-parts":[[2012,8]]}}}