{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,24]],"date-time":"2025-06-24T06:27:07Z","timestamp":1750746427691,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,5]]},"DOI":"10.1109\/ets.2007.10","type":"proceedings-article","created":{"date-parts":[[2007,6,7]],"date-time":"2007-06-07T21:06:24Z","timestamp":1181250384000},"page":"91-96","source":"Crossref","is-referenced-by-count":58,"title":["An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy"],"prefix":"10.1109","author":[{"given":"Philipp","family":"Ohler","sequence":"first","affiliation":[]},{"given":"Sybille","family":"Hellebrand","sequence":"additional","affiliation":[]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TEST.2002.1041777"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/TEST.2004.1387367"},{"key":"18","doi-asserted-by":"crossref","first-page":"222","DOI":"10.1109\/TCAD.1987.1270266","article-title":"On the repair of redundant RAMs","volume":"6","author":"wey","year":"1987","journal-title":"IEEE Trans on CAD"},{"key":"15","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","author":"tarr","year":"1984","journal-title":"Electronics"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/DATE.2006.243969"},{"key":"13","first-page":"35","article-title":"Yield Analysis for Repairable Embedded Memories","author":"seghal","year":"2003","journal-title":"Proc IEEE European Test Workshop"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/MTDT.2001.945228"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TEST.1999.805644"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/DDECS.2007.4295278"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/MDT.1985.294737"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/MDT.2003.1198687"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/92.924057"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/TEST.1999.805645"},{"key":"10","doi-asserted-by":"crossref","first-page":"742","DOI":"10.1109\/TVLSI.2005.848824","article-title":"A built-in self-repair design for RAMs with 2-D redundancy","volume":"13","author":"li","year":"2005","journal-title":"IEEE Trans on VLSI Systems"},{"year":"2005","journal-title":"Edition","key":"7"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/TR.2003.821925"},{"key":"5","article-title":"Computer Algorithms in C++","author":"horowitz","year":"0","journal-title":"New York Computer Science Press 1998 (2nd printing)"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/MTDT.2004.1327984"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/DAC.1986.1586118"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/TEST.2000.894250"}],"event":{"name":"12th IEEE European Test Symposium","start":{"date-parts":[[2007,5,20]]},"location":"Freiburg, Germany","end":{"date-parts":[[2007,5,24]]}},"container-title":["12th IEEE European Test Symposium (ETS'07)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4221553\/4221554\/04221579.pdf?arnumber=4221579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T18:30:21Z","timestamp":1497724221000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4221579\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,5]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/ets.2007.10","relation":{},"ISSN":["1530-1877"],"issn-type":[{"type":"print","value":"1530-1877"}],"subject":[],"published":{"date-parts":[[2007,5]]}}}