{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:45:08Z","timestamp":1776530708494,"version":"3.51.2"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/ats.2015.25","type":"proceedings-article","created":{"date-parts":[[2016,3,3]],"date-time":"2016-03-03T22:17:51Z","timestamp":1457043471000},"page":"103-108","source":"Crossref","is-referenced-by-count":8,"title":["Logic\/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch"],"prefix":"10.1109","author":[{"given":"K.","family":"Asada","sequence":"first","affiliation":[]},{"given":"X.","family":"Wen","sequence":"additional","affiliation":[]},{"given":"S.","family":"Holst","sequence":"additional","affiliation":[]},{"given":"K.","family":"Miyase","sequence":"additional","affiliation":[]},{"given":"S.","family":"Kajihara","sequence":"additional","affiliation":[]},{"given":"M. A.","family":"Kochte","sequence":"additional","affiliation":[]},{"given":"E.","family":"Schneider","sequence":"additional","affiliation":[]},{"given":"H.-J.","family":"Wunderlich","sequence":"additional","affiliation":[]},{"given":"J.","family":"Qian","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Calibrating Clock Stretch during AC Scan Test","author":"rearick","year":"0"},{"key":"ref11","article-title":"On-Chip Timing Uncertainty Measurements on IBM Microprocessors","author":"franch","year":"0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783778"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401548"},{"key":"ref14","first-page":"1031","article-title":"Impact of Multiple-Detect Tesc Patterns on Product Oualitv","author":"benware","year":"0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139145"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.201"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584088"},{"key":"ref6","first-page":"265","article-title":"On Low-Capture-Power Test Generation for Scan Testing","author":"we-n","year":"2005","journal-title":"Proc IEEE VLSI Test Svmp"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref8","author":"girard","year":"2009","journal-title":"Power-Aware Testing and Test Strategies for Low Power Devices"},{"key":"ref7","article-title":"Power-Aware Test: Challenges and Solutions","author":"ravi","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2200029"},{"key":"ref1","author":"walker","year":"2007","journal-title":"Delay Testing in System-on-Chip Test Architectures"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.52"}],"event":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","location":"Mumbai, India","start":{"date-parts":[[2015,11,22]]},"end":{"date-parts":[[2015,11,25]]}},"container-title":["2015 IEEE 24th Asian Test Symposium (ATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7421875\/7422217\/07422243.pdf?arnumber=7422243","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:58:42Z","timestamp":1489888722000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7422243\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ats.2015.25","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}