{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:42:39Z","timestamp":1729662159473,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/ats.2010.24","type":"proceedings-article","created":{"date-parts":[[2011,1,17]],"date-time":"2011-01-17T21:12:41Z","timestamp":1295298761000},"page":"87-93","source":"Crossref","is-referenced-by-count":12,"title":["Variation-Aware Fault Modeling"],"prefix":"10.1109","author":[{"given":"Fabian","family":"Hopsch","sequence":"first","affiliation":[{"name":"Fraunhofer IIS\/EAS, Dresden, Germany"}]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[{"name":"Univ. of Freiburg, Freiburg, Germany"}]},{"given":"Sybille","family":"Hellebrand","sequence":"additional","affiliation":[{"name":"Univ. of Paderborn, Paderborn, Germany"}]},{"given":"Ilia","family":"Polian","sequence":"additional","affiliation":[{"name":"Univ. of Passau, Passau, Germany"}]},{"given":"Bernd","family":"Straube","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS\/EAS, Dresden, Germany"}]},{"given":"Wolfgang","family":"Vermeiren","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS\/EAS, Dresden, Germany"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"Univ. of Stuttgart, Stuttgart, Germany"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700627"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630004"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232032"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2007.09.001"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687480"},{"key":"ref34","first-page":"31","article-title":"On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design","author":"zeng","year":"2004","journal-title":"Proc Int'l Test Conf"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355741"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/81.735442"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2021728"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1377-9","author":"khare","year":"1996","journal-title":"From Contamination to Defects Faults and Yield Loss"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008351601024"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811442"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"1465","DOI":"10.1109\/TCAD.2007.891373","article-title":"Statistical Test Development for Analog Circuits Under High Process Variations","volume":"26","author":"liu","year":"2007","journal-title":"IEEE Trans on CAD of Integrated Circuits and Systems (TCAD)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232031"},{"key":"ref18","first-page":"12","article-title":"A New Performance Characterization of Transient Analysis Method","volume":"1","author":"peralta","year":"2009","journal-title":"International Journal of Electronics Communications and Computer Engineering (IJECCE)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207872"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"967","DOI":"10.1145\/1403375.1403610","article-title":"Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style","author":"stefano","year":"2008","journal-title":"Proceedings of the Design Automation and Test in Europe (DATE)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913191"},{"journal-title":"Statistical Analysis and Optimization for VLSI Timing and Power","year":"2005","author":"srivastava","key":"ref27"},{"journal-title":"Nangate 45nm open cell library","year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557077"},{"key":"ref29","article-title":"Analogue fault simulation by aFSIM","author":"straube","year":"2000","journal-title":"Design Automation and Test in Europe Conference and Exhibition 2000"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5006-6"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1007\/0-387-29409-0","article-title":"Advances in Electronic Testing: Challenges and Methodologies","volume":"27","author":"gizopoulos","year":"2006","journal-title":"ser Frontiers in Electronic Testing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207759"},{"journal-title":"Proc Design Automation and Test in Europe","article-title":"New Techniques for the Design and Test of Nanoscale Electronics","year":"2009","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1998.732184"},{"year":"2009","key":"ref1","article-title":"International Technology Roadmap for Semiconductors"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"650","DOI":"10.1145\/343647.343883","article-title":"Parametric Fault Simulation and Test Vector Generation","author":"saab","year":"2000","journal-title":"Proc Design Automation Test Eur DATE Conf 2000"},{"key":"ref22","article-title":"Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL","author":"santos","year":"1999","journal-title":"Design Automation and Test in Europe"},{"key":"ref21","article-title":"Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits","volume":"34","author":"sachdev","year":"2006","journal-title":"ser Frontiers in Electronic Testing"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090907"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584088"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1023\/B:JETT.0000009310.48706.b7"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294793"}],"event":{"name":"2010 19th Asian Test Symposium (ATS)","start":{"date-parts":[[2010,12,1]]},"location":"Shanghai, China","end":{"date-parts":[[2010,12,4]]}},"container-title":["2010 19th IEEE Asian Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5689827\/5692210\/05692228.pdf?arnumber=5692228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,17]],"date-time":"2021-11-17T14:39:51Z","timestamp":1637159991000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5692228\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/ats.2010.24","relation":{},"subject":[],"published":{"date-parts":[[2010,12]]}}}