{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:35:52Z","timestamp":1729661752755,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/aspdac.1998.669502","type":"proceedings-article","created":{"date-parts":[[2002,11,27]],"date-time":"2002-11-27T11:45:36Z","timestamp":1038397536000},"page":"367-372","source":"Crossref","is-referenced-by-count":1,"title":["A performance maximization algorithm to design ASIPs under the constraint of chip area including RAM and ROM sizes"],"prefix":"10.1109","author":[{"family":"Nguyen Ngoc Binh","sequence":"first","affiliation":[]},{"given":"M.","family":"Imai","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Takeuchi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1994.336721"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1145\/196244.196250","article-title":"synthesis of instruction sets for pipelined microprocessors","author":"huang","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1995.527405"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/224818.224845"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240618"},{"key":"ref15","first-page":"135","article-title":"The Satsuki Integrated Processor Synthesis and Compiler Generation System","author":"shackleford","year":"1996","journal-title":"Proc SASIMI 96"},{"key":"ref16","first-page":"151","article-title":"Synthesis and Analysis of an Industrial Embedded Microcontroller","author":"huang","year":"1997","journal-title":"Proc IEEE ASP DAC 97"},{"key":"ref17","first-page":"59","article-title":"A Pipeline Scheduling Algorithm for Instruction Set Processor Design Optimization","author":"binh","year":"1994","journal-title":"Proc of the APCHDL-94"},{"year":"0","key":"ref18"},{"journal-title":"Using and Porting GNU CC","year":"1991","author":"stallman","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545631"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240616"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/54.245964"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/54.232470"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1992.246257"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.248879"},{"key":"ref2","first-page":"126","article-title":"A New HW\/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs","author":"b\ufffdnh","year":"1996","journal-title":"EURO-DAC 96 Proc"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1007\/BF00134682","volume":"1","author":"camposano","year":"1996","journal-title":"Design Automation for Embedded System"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580109"}],"event":{"name":"1998 Asia and South Pacific Design Automation Conference","acronym":"ASPDAC-98","location":"Yokohama, Japan"},"container-title":["Proceedings of 1998 Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx4\/5474\/14742\/00669502.pdf?arnumber=669502","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T11:17:52Z","timestamp":1497525472000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/669502\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/aspdac.1998.669502","relation":{},"subject":[]}}