{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T21:43:38Z","timestamp":1765057418566},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[1998,5,1]],"date-time":"1998-05-01T00:00:00Z","timestamp":893980800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[1998,5]]},"DOI":"10.1109\/4.668996","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:00:39Z","timestamp":1030219239000},"page":"800-806","source":"Crossref","is-referenced-by-count":10,"title":["An access-sequence control scheme to enhance random-access performance of embedded DRAM's"],"prefix":"10.1109","volume":"33","author":[{"given":"K.","family":"Ayukawa","sequence":"first","affiliation":[]},{"given":"T.","family":"Watanabe","sequence":"additional","affiliation":[]},{"given":"S.","family":"Narita","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.406409"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1996.507709"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.568823"},{"key":"ref13","article-title":"an access-sequence control scheme to enhance random access performance of embedded dram's","author":"ayukawa","year":"1997","journal-title":"1997 Symp VLSI Circuits Dig"},{"key":"ref4","article-title":"low-power and high-speed advantages of dram-logic integration for multimedia systems","year":"1997","journal-title":"IEICE Trans Electron"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/72.217179"},{"key":"ref6","first-page":"302","article-title":"a 10-mb 3-d frame buffer memory with <formula><tex>$z$<\/tex><\/formula>-compare and alpha-blend units","author":"inoue","year":"1995","journal-title":"IEEE ISSCC 95 Dig"},{"key":"ref5","first-page":"1181","article-title":"3-d cg media chip: an experimental single-chip architecture for three-dimensional computer graphics","year":"1994","journal-title":"IEICE Trans Electron"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488722"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1995.535564"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1992.591879"},{"key":"ref1","first-page":"20.3.1","article-title":"a 72-k cmos channelless gate array with embedded 1-mbit dynamic ram","author":"sawada","year":"1988","journal-title":"CICC Dig"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488577"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx4\/4\/14629\/00668996.pdf?arnumber=668996","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:07:13Z","timestamp":1638216433000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/668996\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,5]]},"references-count":13,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/4.668996","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[1998,5]]}}}