{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:47:22Z","timestamp":1759146442297},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[1997,4,1]],"date-time":"1997-04-01T00:00:00Z","timestamp":859852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[1997,4]]},"DOI":"10.1109\/4.563678","type":"journal-article","created":{"date-parts":[[2002,8,24]],"date-time":"2002-08-24T20:00:39Z","timestamp":1030219239000},"page":"563-573","source":"Crossref","is-referenced-by-count":60,"title":["Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems"],"prefix":"10.1109","volume":"32","author":[{"family":"Fang-Shi Lai","sequence":"first","affiliation":[]},{"family":"Wei Hwang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1982.1051786"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052435"},{"key":"ref12","author":"sze","year":"1981","journal-title":"Physics of Semiconductor Devices"},{"key":"ref13","first-page":"144","article-title":"pass-transistor networks optimize n-mos logic","author":"whitaker","year":"1983","journal-title":"Electron"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052339"},{"key":"ref15","author":"winkel","year":"1980","journal-title":"The Art of Digital Design"},{"key":"ref16","author":"feng","year":"1986"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.488002"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1995.535283"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1994.379719"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1993.280071"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052767"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1984.1156629"},{"key":"ref8","first-page":"6148","article-title":"testing scheme for differential cascode voltage switch circuits","volume":"27","author":"montoye","year":"1985","journal-title":"IBM Tech Disclosure Bulletin"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052651"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1109\/4.52161","article-title":"a 3.8 ns cmos 16 <formula><tex>$\\times$<\/tex><\/formula> 16 multiplier using complementary pass-gate transistor logic","volume":"25","author":"yano","year":"1990","journal-title":"IEEE J Solid-Sate Circuits"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-2285-6","author":"annaratone","year":"1986","journal-title":"Digital CMOS Circuit Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.1993.263680"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx1\/4\/12250\/00563678.pdf?arnumber=563678","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:07:03Z","timestamp":1638216423000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/563678\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,4]]},"references-count":18,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/4.563678","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[1997,4]]}}}