{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T14:50:51Z","timestamp":1747147851030,"version":"3.40.5"},"reference-count":23,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2024,4,2]],"date-time":"2024-04-02T00:00:00Z","timestamp":1712016000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[2024,10]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper presents a comprehensive study of Class\u2010\u2010E\/F<jats:sub>2<\/jats:sub> and inverse Class\u2010\u2010F power amplifiers (PAs) designed for 35\u201342\u2009GHz millimeter\u2010wave applications, utilizing a 130\u2009nm CMOS process. The proposed RF PAs are well suited for wide frequency\u2010band millimeter\u2010wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E\/F<jats:sub>2<\/jats:sub> architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class\u2010\u2010F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E\/F<jats:sub>2<\/jats:sub> and inverse Class\u2010\u2010F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class\u2010\u2010AB stage and a power stage constructed based on either the Class E\/F2 architecture or inverse Class\u2010\u2010F topology, utilizing harmonic termination networks at the output load. Two new designs of high\u2010Q factor on\u2010chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter\u2010stage matching is facilitated by employing two novel on\u2010chip transformers designed for maximum power transfer. Additionally, an inter\u2010stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on\u2010chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S\u2010parameter files (SNP files) of the designed on\u2010chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E\/F<jats:sub>2<\/jats:sub> power amplifier achieves a constant power of 14.9\u00a0dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74\u2009dB. In contrast, the suggested inverse Class\u2010\u2010F power amplifier attains a constant power of 15.4\u00a0dBm, a peak PAE of 12.6%, and a maximum gain of 14.8\u00a0dB. The DC power consumption is 73 and 66\u2009mW for the proposed Class E\/F<jats:sub>2<\/jats:sub> and inverse Class\u2010\u2010F PAs, respectively, while their active sizes are 0.14 and 0.2\u00a0mm<jats:sup>2<\/jats:sup>.<\/jats:p>","DOI":"10.1002\/cta.4030","type":"journal-article","created":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T01:55:26Z","timestamp":1712109326000},"page":"4878-4902","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Comprehensive study of Class\u2010\u2010E\/F<sub>2<\/sub> and inverse Class\u2010\u2010F power amplifiers for mm\u2010Wave systems utilizing 130\u2009nm CMOS process"],"prefix":"10.1002","volume":"52","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8501-1101","authenticated-orcid":false,"given":"Marwa","family":"Mansour","sequence":"first","affiliation":[{"name":"Microelectronics Department Electronics Research Institute (ERI)  Cairo Egypt"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0555-7142","authenticated-orcid":false,"given":"Islam","family":"Mansour","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Shoubra Faculty of Engineering Benha University  Cairo Egypt"}]}],"member":"311","published-online":{"date-parts":[[2024,4,2]]},"reference":[{"key":"e_1_2_8_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2008.916815"},{"key":"e_1_2_8_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00034\u2010020\u201001525\u20104"},{"volume-title":"Switchmode RF Power Amplifiers","year":"2007","author":"Grebennikov A","key":"e_1_2_8_4_1"},{"key":"e_1_2_8_5_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.3363"},{"key":"e_1_2_8_6_1","doi-asserted-by":"publisher","DOI":"10.3390\/app13042501"},{"key":"e_1_2_8_7_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126617501912"},{"key":"e_1_2_8_8_1","first-page":"1","volume-title":"IEEE MTT\u2010S Int. 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