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Realized in 28\u2010nm CMOS technology, the proposed RX incorporates a wideband low\u2010noise amplifier (LNA), double\u2010balanced passive mixers for the dual down\u2010conversion, a differential power divider, a differential intermediate frequency filters, a current\u2010mode\u2010logic divider\u2010by\u20102, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four\u2010stage LNA is devised to realize the high gain and low noise figure (NF) with a common\u2010gate input stage and three pseudodifferential common\u2010source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer\u2010based matching networks with the peak\u2010staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double\u2010balanced mixers are implemented with a highly symmetrical layout for broadband down\u2010conversion. Simulation results show that the mm\u2010Wave RX front\u2010end exhibits a BW ranging from 90 to 115\u2009GHz. The simulated NF of our RX is 4.7\u00a0dB at 86\u2009GHz. With a supply voltage of 1\u00a0V, the presented RX consumes 88.2\u2010mW power and occupies a chip size of 1.6\u2009\u00d7\u20090.5\u00a0mm<jats:sup>2<\/jats:sup> including all the testing pads. The proposed RX is suitable for W\u2010band imaging systems.<\/jats:p>","DOI":"10.1002\/cta.3509","type":"journal-article","created":{"date-parts":[[2022,11,23]],"date-time":"2022-11-23T06:53:05Z","timestamp":1669186385000},"page":"1530-1547","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 90\u2010 to 115\u2010GHz superheterodyne receiver front\u2010end for W\u2010band imaging system in 28\u2010nm complementary metal\u2010oxide\u2010semiconductor"],"prefix":"10.1002","volume":"51","author":[{"given":"Xi","family":"Wang","sequence":"first","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"given":"Dong","family":"Wei","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"given":"Zhiyang","family":"Zhang","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"given":"Tianxiang","family":"Wu","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"given":"Xu","family":"Chen","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2794-1324","authenticated-orcid":false,"given":"Yong","family":"Chen","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of Analog and Mixed\u2010Signal VLSI and IME\/ECE\u2010FST University of Macau  Macau China"}]},{"given":"Junyan","family":"Ren","sequence":"additional","affiliation":[{"name":"State\u2010Key Laboratory of ASIC and System Fudan University  Shanghai China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9144-9078","authenticated-orcid":false,"given":"Shunli","family":"Ma","sequence":"additional","affiliation":[{"name":"State\u2010Key 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