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A TSPCL\u2010NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull\u2010down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16\u2010bit TSPCL\u2010NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power\u2010delay product can be improved by 5.92% as compared with the state\u2010of\u2010the art 16\u2010bit XOR\u2010NT Manchester adder design under TSMC 90\u2009nm CMOS process. Copyright \u00a9 2014 John Wiley &amp; Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cta.1976","type":"journal-article","created":{"date-parts":[[2014,1,10]],"date-time":"2014-01-10T16:57:06Z","timestamp":1389373026000},"page":"854-865","source":"Crossref","is-referenced-by-count":12,"title":["Noise\u2010tolerant dynamic CMOS circuits design by using true single\u2010phase clock latching technique"],"prefix":"10.1002","volume":"43","author":[{"given":"I\u2010Chyn","family":"Wey","sequence":"first","affiliation":[{"name":"Graduate Institute of Electrical Engineering, Electrical Engineering Department, Green Technology Research Center, and Healthy\u2010Aging Research Center Chang\u2010Gung University Taiwan"}]},{"given":"Chun\u2010Wei","family":"Chang","sequence":"additional","affiliation":[{"name":"Graduate Institute of Electrical Engineering Chang\u2010Gung University Taiwan"}]},{"given":"Yu\u2010Cheng","family":"Liao","sequence":"additional","affiliation":[{"name":"Graduate Institute of Electrical Engineering Chang\u2010Gung University Taiwan"}]},{"given":"Heng\u2010Jui","family":"Chou","sequence":"additional","affiliation":[{"name":"Graduate Institute of Electrical Engineering Chang\u2010Gung University Taiwan"}]}],"member":"311","published-online":{"date-parts":[[2014,1,10]]},"reference":[{"key":"e_1_2_6_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2012.2185961"},{"key":"e_1_2_6_3_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2009.0099"},{"key":"e_1_2_6_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2107171"},{"key":"e_1_2_6_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025591"},{"key":"e_1_2_6_6_1","doi-asserted-by":"crossref","unstructured":"AnisMH AllamMW ElmasryMI.High\u2010speed dynamic logic styles for scaled\u2010down CMOS and MTCMOS technologies. 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